Merge branch 'v4-dev' of ohwr.org:white-rabbit/wr-switch-hdl into v4-dev

a852642d · Maciej Lipinski · 52a05044 · 88da8ad9 · a852642d · 18fa7851
Commit a852642d authored Mar 27, 2013 by Maciej Lipinski
16 changed files
--- a/Manifest.py
+++ b/Manifest.py
@@ -7,6 +7,7 @@ modules = { "local" : [
 				"modules/wrsw_tru",
 				"modules/wrsw_tatsu",
 				"modules/wrsw_pstats",
+        "modules/wrsw_hwdu",
 				"platform/virtex6/chipscope",
 				"platform/xilinx"],
 				"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ]

--- a/general-cores @ 18fa7851
+++ b/general-cores @ 18fa7851
-Subproject commit 4481315c88ba746c31f71e4128aac5a1df0022fd
+Subproject commit 18fa7851a47d149d5562a92e0fa36b05286628e0
--- a/wr-cores @ 67cd9ce0
+++ b/wr-cores @ 67cd9ce0
-Subproject commit 0362f910fa5f7268c6101ae0940553c7bab02bfc
+Subproject commit 67cd9ce053e3b3a43f0f4d29b1b03bb5ec61861f
--- a/modules/wrsw_hwdu/Manifest.py
+++ b/modules/wrsw_hwdu/Manifest.py
+files = ["wrsw_hwdu.vhd", "hwdu_wishbone_slave.vhd", "hwdu_wbgen2_pkg.vhd", "xwrsw_hwdu.vhd"]
--- a/modules/wrsw_hwdu/build_wb.sh
+++ b/modules/wrsw_hwdu/build_wb.sh
+#!/bin/bash
+
+mkdir -p doc
+wbgen2 -D ./doc/wrsw_hwdu.html -C hwdu_regs.h -V hwdu_wishbone_slave.vhd --cstyle struct --lang vhdl -K ../../sim/regs/hwdu_regs.vh -p hwdu_wbgen2_pkg.vhd --hstyle record wrsw_hwdu.wb 
--- a/modules/wrsw_hwdu/doc/wrsw_hwdu.html
+++ b/modules/wrsw_hwdu/doc/wrsw_hwdu.html
--- a/modules/wrsw_hwdu/hwdu_wbgen2_pkg.vhd
+++ b/modules/wrsw_hwdu/hwdu_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Switch Hardware Debugging Unit
+---------------------------------------------------------------------------------------
+-- File           : hwdu_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from wrsw_hwdu.wb
+-- Created        : Tue Mar 26 09:59:28 2013
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwdu.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package hwdu_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_hwdu_in_registers is record
+    cr_rd_err_i                              : std_logic;
+    cr_rd_en_i                               : std_logic;
+    reg_val_i                                : std_logic_vector(31 downto 0);
+    end record;
+  
+  constant c_hwdu_in_registers_init_value: t_hwdu_in_registers := (
+    cr_rd_err_i => '0',
+    cr_rd_en_i => '0',
+    reg_val_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_hwdu_out_registers is record
+      cr_adr_o                                 : std_logic_vector(15 downto 0);
+      cr_rd_en_o                               : std_logic;
+      cr_rd_en_load_o                          : std_logic;
+      end record;
+    
+    constant c_hwdu_out_registers_init_value: t_hwdu_out_registers := (
+      cr_adr_o => (others => '0'),
+      cr_rd_en_o => '0',
+      cr_rd_en_load_o => '0'
+      );
+    function "or" (left, right: t_hwdu_in_registers) return t_hwdu_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body hwdu_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if(x = 'X' or x = 'U') then
+return '0';
+else
+return x;
+end if; 
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_hwdu_in_registers) return t_hwdu_in_registers is
+variable tmp: t_hwdu_in_registers;
+begin
+tmp.cr_rd_err_i := f_x_to_zero(left.cr_rd_err_i) or f_x_to_zero(right.cr_rd_err_i);
+tmp.cr_rd_en_i := f_x_to_zero(left.cr_rd_en_i) or f_x_to_zero(right.cr_rd_en_i);
+tmp.reg_val_i := f_x_to_zero(left.reg_val_i) or f_x_to_zero(right.reg_val_i);
+return tmp;
+end function;
+end package body;
--- a/modules/wrsw_hwdu/hwdu_wishbone_slave.vhd
+++ b/modules/wrsw_hwdu/hwdu_wishbone_slave.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Switch Hardware Debugging Unit
+---------------------------------------------------------------------------------------
+-- File           : hwdu_wishbone_slave.vhd
+-- Author         : auto-generated by wbgen2 from wrsw_hwdu.wb
+-- Created        : Tue Mar 26 09:59:28 2013
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwdu.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.hwdu_wbgen2_pkg.all;
+
+
+entity hwdu_wishbone_slave is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(0 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    regs_i                                   : in     t_hwdu_in_registers;
+    regs_o                                   : out    t_hwdu_out_registers
+  );
+end hwdu_wishbone_slave;
+
+architecture syn of hwdu_wishbone_slave is
+
+signal hwdu_cr_adr_int                          : std_logic_vector(15 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal bwsel_reg                                : std_logic_vector(3 downto 0);
+signal rwaddr_reg                               : std_logic_vector(0 downto 0);
+signal ack_in_progress                          : std_logic      ;
+signal wr_int                                   : std_logic      ;
+signal rd_int                                   : std_logic      ;
+signal allones                                  : std_logic_vector(31 downto 0);
+signal allzeros                                 : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+  wrdata_reg <= wb_dat_i;
+  bwsel_reg <= wb_sel_i;
+  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+  allones <= (others => '1');
+  allzeros <= (others => '0');
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      hwdu_cr_adr_int <= "0000000000000000";
+      regs_o.cr_rd_en_load_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          regs_o.cr_rd_en_load_o <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.cr_rd_en_load_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(0) is
+          when '0' => 
+            if (wb_we_i = '1') then
+              hwdu_cr_adr_int <= wrdata_reg(15 downto 0);
+              regs_o.cr_rd_en_load_o <= '1';
+            end if;
+            rddata_reg(15 downto 0) <= hwdu_cr_adr_int;
+            rddata_reg(30) <= regs_i.cr_rd_err_i;
+            rddata_reg(31) <= regs_i.cr_rd_en_i;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when '1' => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.reg_val_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Address of the register
+  regs_o.cr_adr_o <= hwdu_cr_adr_int;
+-- Read error
+-- Read register value
+  regs_o.cr_rd_en_o <= wrdata_reg(31);
+-- register value
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
--- a/modules/wrsw_hwdu/wrsw_hwdu.vhd
+++ b/modules/wrsw_hwdu/wrsw_hwdu.vhd
+-------------------------------------------------------------------------------
+-- Title      : Hardware Debugging Unit
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wrsw_hwdu.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Created    : 2013-03-26
+-- Last update: 2013-03-26
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Debugging module, allows reading the content of selected registers inside 
+-- WR Switch GW through Wishbone interface.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-03-26  0.1      greg.d          Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.hwdu_wbgen2_pkg.all;
+
+entity wrsw_hwdu is
+  generic (
+    g_nregs  : integer := 1;
+    g_rwidth : integer := 32);
+  port(
+    rst_n_i : in std_logic;
+    clk_i   : in std_logic;
+
+    dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+
+    wb_adr_i   : in  std_logic_vector(0 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+    wb_int_o   : out std_logic);
+end wrsw_hwdu;
+
+architecture behav of wrsw_hwdu is
+
+  component hwdu_wishbone_slave
+    port (
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(0 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      regs_i     : in  t_hwdu_in_registers;
+      regs_o     : out t_hwdu_out_registers
+    );
+  end component;
+
+  signal wb_regs_in  : t_hwdu_in_registers;
+  signal wb_regs_out : t_hwdu_out_registers;
+
+  type   t_rd_st is (IDLE, READ);
+  signal rd_state : t_rd_st;
+
+  signal rd_val        : std_logic_vector(g_rwidth-1 downto 0);
+  signal rd_err, rd_en : std_logic;
+
+begin
+
+  U_WB_Slave : hwdu_wishbone_slave
+    port map(
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_i,
+      wb_adr_i   => wb_adr_i,
+      wb_dat_i   => wb_dat_i,
+      wb_dat_o   => wb_dat_o,
+      wb_cyc_i   => wb_cyc_i,
+      wb_sel_i   => wb_sel_i,
+      wb_stb_i   => wb_stb_i,
+      wb_we_i    => wb_we_i,
+      wb_ack_o   => wb_ack_o,
+      wb_stall_o => wb_stall_o,
+      regs_i     => wb_regs_in,
+      regs_o     => wb_regs_out
+    );
+  wb_int_o <= '0';
+
+  wb_regs_in.reg_val_i(g_rwidth-1 downto 0) <= rd_val;
+  GEN_regval : if g_rwidth < 32 generate
+    wb_regs_in.reg_val_i(31 downto g_rwidth) <= (others => '0');
+  end generate;
+
+  wb_regs_in.cr_rd_err_i <= rd_err;
+  wb_regs_in.cr_rd_en_i  <= rd_en;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if(rst_n_i = '0') then
+        rd_state <= IDLE;
+        rd_en    <= '0';
+        rd_err   <= '0';
+      else
+        case(rd_state) is
+          when IDLE =>
+            if(wb_regs_out.cr_rd_en_o = '1' and wb_regs_out.cr_rd_en_load_o = '1') then
+              rd_en    <= '1';
+              rd_state <= READ;
+            end if;
+          when READ =>
+            rd_en    <= '0';
+            rd_state <= IDLE;
+            if(to_integer(unsigned(wb_regs_out.cr_adr_o)) > g_nregs-1) then
+              rd_err <= '1';
+            else
+              rd_err <= '0';
+              --get part of dbg_regs input vector
+              rd_val <= dbg_regs_i((to_integer(unsigned(wb_regs_out.cr_adr_o))+1)*g_rwidth-1 downto
+                        to_integer(unsigned(wb_regs_out.cr_adr_o))*g_rwidth);
+            end if;
+
+          when others =>
+            rd_state <= IDLE;
+        end case;
+      end if;
+    end if;
+  end process;
+
+
+end behav;
--- a/modules/wrsw_hwdu/wrsw_hwdu.wb
+++ b/modules/wrsw_hwdu/wrsw_hwdu.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+-- White-Rabbit Hardware Debugging Unit
+-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+--
+-- Use wbgen2 to generate code, documentation and more.
+-- wbgen2 is available at:
+-- http://www.ohwr.org/projects/wishbone-gen
+--
+
+peripheral {
+ 
+  name = "WR Switch Hardware Debugging Unit";
+  description = "The module is used for reading the value of registers from inside of WR Switch. Usefull for debugging during development.";
+  hdl_entity = "hwdu_wishbone_slave";
+  prefix = "hwdu";
+
+
+  reg {
+    name = "Control Register";
+    prefix = "CR";
+
+    field {
+        name = "Address of the register";
+        description = "Which register (among those connected to HWDU) will be read";
+        prefix = "ADR";
+        size = 16;
+        type = SLV;
+        access_bus = READ_WRITE;
+        access_dev = READ_ONLY;
+    };
+
+    field {
+        name = "Read error";
+        description = "read 1: read error, provided address is out of range \
+                       read 0: read done successfully";
+        prefix = "RD_ERR";
+        type = BIT;
+        align = 30;
+        access_bus = READ_ONLY;
+        access_dev = WRITE_ONLY;
+    };
+
+    field {
+       name = "Read register value";
+       description = "write 1: read the content \
+                      write 0: no effect \
+                      read  1: reading in progress \
+                      read  0: reading done, register value available";
+       prefix = "RD_EN";
+       
+       type = BIT;
+       align = 31;
+       access_dev = READ_WRITE;
+       access_bus = READ_WRITE;
+       load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "Value of the requested register";
+    description = "The value of the register under ADR from the Control Register";
+    prefix = "REG_VAL";
+
+    field {
+      name = "register value";
+      size = 32;
+      type = SLV;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
+};
--- a/modules/wrsw_hwdu/xwrsw_hwdu.vhd
+++ b/modules/wrsw_hwdu/xwrsw_hwdu.vhd
+-------------------------------------------------------------------------------
+-- Title      : Hardware Debugging Unit wrapper
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : xwrsw_hwdu.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Created    : 2013-03-26
+-- Last update: 2013-03-26
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Record-based wrapper for wrsw_hwdu module.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-03-26  0.1      greg.d          Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+
+entity xwrsw_hwdu is
+  generic (
+    g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity : t_wishbone_address_granularity := BYTE;
+    g_nregs               : integer                        := 1;
+    g_rwidth              : integer                        := 32);
+  port(
+    rst_n_i : in std_logic;
+    clk_i   : in std_logic;
+
+    dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+
+    wb_i : in  t_wishbone_slave_in;
+    wb_o : out t_wishbone_slave_out);
+end xwrsw_hwdu;
+
+architecture behav of xwrsw_hwdu is
+
+  component wrsw_hwdu
+    generic (
+      g_nregs  : integer := 1;
+      g_rwidth : integer := 32);
+    port(
+      rst_n_i : in std_logic;
+      clk_i   : in std_logic;
+
+      dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+
+      wb_adr_i   : in  std_logic_vector(0 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      wb_int_o   : out std_logic);
+  end component;
+
+  signal wb_in  : t_wishbone_slave_in;
+  signal wb_out : t_wishbone_slave_out;
+
+begin
+
+  U_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i => clk_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => wb_i,
+      slave_o   => wb_o,
+      master_i  => wb_out,
+      master_o  => wb_in);
+
+  wb_out.err <= '0';
+  wb_out.rty <= '0';
+
+  U_Wrapped_HWDU : wrsw_hwdu
+    generic map(
+      g_nregs  => g_nregs,
+      g_rwidth => g_rwidth)
+    port map(
+      rst_n_i    => rst_n_i,
+      clk_i      => clk_i,
+      dbg_regs_i => dbg_regs_i,
+      wb_adr_i   => wb_in.adr(0 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_stall_o => wb_out.stall,
+      wb_int_o   => wb_out.int
+    );
+
+end behav;
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -24,7 +24,8 @@ entity scb_top_bare is
    g_simulation      : boolean := false;
    g_without_network : boolean := false;
    g_with_TRU        : boolean := false;
-    g_with_TATSU      : boolean := false
+    g_with_TATSU      : boolean := false;
+    g_with_HWDU       : boolean := false
    );
  port (
    sys_rst_n_i : in std_logic;         -- global reset
@@ -130,7 +131,7 @@ end scb_top_bare;

 architecture rtl of scb_top_bare is

-  constant c_NUM_WB_SLAVES : integer := 14;
+  constant c_NUM_WB_SLAVES : integer := 15;
  constant c_NUM_PORTS     : integer := g_num_ports;
  constant c_MAX_PORTS     : integer := 18;
  constant c_NUM_GL_PAUSE  : integer := 2; -- number of output global PAUSE sources for SWcore
@@ -156,11 +157,13 @@ architecture rtl of scb_top_bare is
  constant c_SLAVE_TRU          : integer := 10;
  constant c_SLAVE_TATSU        : integer := 11;
  constant c_SLAVE_PSTATS       : integer := 12;
-  constant c_SLAVE_DUMMY        : integer := 13;
+  constant c_SLAVE_HWDU         : integer := 13;
+  constant c_SLAVE_DUMMY        : integer := 14;

  constant c_cnx_base_addr : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
    (
-      x"00070000",                      -- Dummy counters
+      x"00071000",                      -- Dummy counters
+      x"00070000",                      -- HWDU
      x"00059000",                      -- PStats counters
      x"00058000",                      -- TATSU
      x"00057000",                      -- TRU
@@ -178,6 +181,7 @@ architecture rtl of scb_top_bare is

  constant c_cnx_base_mask : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
    (x"000ff000",
+     x"000ff000",
     x"000ff000",
     x"000ff000",
     x"000ff000",
@@ -931,6 +935,33 @@ begin
                ep_events ((i+1)*c_epevents_sz-1 downto i*c_epevents_sz);
  end generate gen_events_assemble;

+  --=====================================--
+  --               HWDU                  --
+  --=====================================--
+  gen_HWDU: if(g_with_HWDU = true) generate
+    U_HWDU : xwrsw_hwdu
+      generic map(
+        g_interface_mode      => PIPELINED,
+        g_address_granularity => BYTE,
+        g_nregs => 1)
+      port map(
+        rst_n_i => rst_n_periph,
+        clk_i   => clk_sys,
+
+        dbg_regs_i  => (others=>'0'),
+
+        wb_i  => cnx_master_out(c_SLAVE_HWDU),
+        wb_o  => cnx_master_in(c_SLAVE_HWDU));
+    end generate;
+    gen_no_HWDU: if(g_with_HWDU = false) generate
+      cnx_master_in(c_SLAVE_HWDU).ack   <= '1';
+      cnx_master_in(c_SLAVE_HWDU).dat   <= x"deadbeef";
+      cnx_master_in(c_SLAVE_HWDU).err   <= '0';
+      cnx_master_in(c_SLAVE_HWDU).stall <= '0';
+      cnx_master_in(c_SLAVE_HWDU).rty   <= '0';
+    end generate;
+
+
  -- debugging for RMONS, not to be included into final release
  gen_dummy_rmon: if(c_DUMMY_RMON = true) generate
    U_DUMMY: dummy_rmon
@@ -955,6 +986,7 @@ begin
  gen_no_dummy_rmon: if(c_DUMMY_RMON = false) generate
    cnx_master_in(c_SLAVE_DUMMY).ack <= '1';
  end generate gen_no_dummy_rmon;
+
  -----------------------------------------------------------------------------
  -- Interrupt assignment
  -----------------------------------------------------------------------------

--- a/top/bare_top/wrsw_components_pkg.vhd
+++ b/top/bare_top/wrsw_components_pkg.vhd
@@ -323,6 +323,23 @@ package wrsw_components_pkg is
      wb_o : out t_wishbone_slave_out );
  end component;

+  component xwrsw_hwdu
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity : t_wishbone_address_granularity := BYTE;
+      g_nregs   : integer := 1;
+      g_rwidth  : integer := 32);
+    port(
+      rst_n_i : in std_logic;
+      clk_i   : in std_logic;
+  
+      dbg_regs_i  : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+  
+      wb_i : in  t_wishbone_slave_in;
+      wb_o : out t_wishbone_slave_out);
+  end component;
+
+
  --TEMP
  component dummy_rmon
    generic(

--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
@@ -220,7 +220,8 @@ package wrsw_top_pkg is
      g_simulation      : boolean;
      g_without_network : boolean;
      g_with_TRU        : boolean  := false;
-      g_with_TATSU      : boolean  := false);
+      g_with_TATSU      : boolean  := false;
+      g_with_HWDU       : boolean  := false);
    port (
      sys_rst_n_i         : in  std_logic;
      clk_startup_i       : in  std_logic;
@@ -382,6 +383,23 @@ package wrsw_top_pkg is
      wb_o : out t_wishbone_slave_out );
  end component;

+  component xwrsw_hwdu
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity : t_wishbone_address_granularity := BYTE;
+      g_nregs   : integer := 1;
+      g_rwidth  : integer := 32);
+    port(
+      rst_n_i : in std_logic;
+      clk_i   : in std_logic;
+  
+      dbg_regs_i  : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
+  
+      wb_i : in  t_wishbone_slave_in;
+      wb_o : out t_wishbone_slave_out);
+  end component;
+
+
  --TEMP
  component dummy_rmon
    generic(

--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -228,7 +228,8 @@ architecture Behavioral of scb_top_synthesis is
      g_simulation      : boolean;
      g_without_network : boolean;
      g_with_TRU        : boolean;
-      g_with_TATSU      : boolean);
+      g_with_TATSU      : boolean;
+      g_with_HWDU       : boolean);
    port (
      sys_rst_n_i         : in  std_logic;
      clk_startup_i       : in  std_logic;
@@ -550,7 +551,8 @@ begin
      g_simulation      => g_simulation,
      g_without_network => false,
      g_with_TRU        => true,
-      g_with_TATSU      => true)
+      g_with_TATSU      => true,
+      g_with_HWDU       => true)
    port map (
      sys_rst_n_i         => sys_rst_n_i,
      clk_startup_i       => clk_sys_startup,

--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -230,7 +230,8 @@ architecture Behavioral of scb_top_synthesis is
      g_simulation      : boolean;
      g_without_network : boolean;
      g_with_TRU        : boolean;
-      g_with_TATSU      : boolean);
+      g_with_TATSU      : boolean;
+      g_with_HWDU       : boolean);
    port (
      sys_rst_n_i         : in  std_logic;
      clk_startup_i       : in  std_logic;
@@ -553,7 +554,8 @@ begin
      g_simulation      => g_simulation,
      g_without_network => false,
      g_with_TRU        => true,
-      g_with_TATSU      => true)
+      g_with_TATSU      => true,
+      g_with_HWDU       => true)
    port map (
      sys_rst_n_i         => sys_rst_n_i,
      clk_startup_i       => clk_sys_startup,