Skip to content

W
White Rabbit Switch - Gateware
Commit af1ec690 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
Browse files
Options

wrsw_watchdog: interface with swcore and wishbone bus

parent 957bd206
Hide whitespace changes
Inline Side-by-side
Showing with 719 additions and 80 deletions
modules/wrsw_shared_types_pkg.vhd
View file @ af1ec690
......@@ -149,4 +149,14 @@ package wrsw_shared_types_pkg is
type t_pause_request_array is array(integer range <>) of t_pause_request;
type t_global_pause_request_array is array(integer range <>) of t_global_pause_request;
type t_swc_fsms is array(integer range <>) of std_logic_vector(3 downto 0);
type t_swc_fsms_array is array(integer range <>) of t_swc_fsms(6 downto 0);
constant c_ALLOC_FSM_IDX : integer := 0;
constant c_TRANS_FSM_IDX : integer := 1;
constant c_RCV_FSM_IDX : integer := 2;
constant c_LL_FSM_IDX : integer := 3;
constant c_PREP_FSM_IDX : integer := 4;
constant c_SEND_FSM_IDX : integer := 5;
constant c_FREE_FSM_IDX : integer := 6;
end wrsw_shared_types_pkg;
modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
View file @ af1ec690
......@@ -45,6 +45,7 @@ use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.wrsw_shared_types_pkg.all;
......@@ -87,7 +88,9 @@ entity swc_multiport_pck_pg_free_module is
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_force_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
mmu_force_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0)
mmu_force_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
wdog_o : out t_swc_fsms_array(g_num_ports-1 downto 0)
);
end swc_multiport_pck_pg_free_module;
......@@ -138,7 +141,9 @@ begin -- syn
mmu_force_free_done_i => mmu_force_free_done_i(i),
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
mmu_force_free_resource_o => mmu_force_free_resource_o((i+1)*g_resource_num_width -1 downto i *g_resource_num_width),
mmu_force_free_resource_valid_o => mmu_force_free_resource_valid_o(i)
mmu_force_free_resource_valid_o => mmu_force_free_resource_valid_o(i),
wdog_o => wdog_o(i)
);
end generate lpd_gen;
......
modules/wrsw_swcore/swc_pck_pg_free_module.vhd
View file @ af1ec690
......@@ -50,6 +50,7 @@ use ieee.numeric_std.all;
library work;
--use work.swc_swcore_pkg.all;
use work.genram_pkg.all;
use work.wrsw_shared_types_pkg.all;
entity swc_pck_pg_free_module is
generic(
......@@ -88,8 +89,9 @@ entity swc_pck_pg_free_module is
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_force_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
mmu_force_free_resource_valid_o : out std_logic
mmu_force_free_resource_valid_o : out std_logic;
wdog_o : out t_swc_fsms
);
......@@ -108,6 +110,7 @@ architecture syn of swc_pck_pg_free_module is
);
signal state : t_state;
signal free_FSM : std_logic_vector(3 downto 0);
signal ib_force_free_done : std_logic;
signal ob_free_done : std_logic;
......@@ -408,5 +411,13 @@ fsm_force_free : process(clk_i, rst_n_i)
mmu_force_free_resource_o <= force_free_resource;
mmu_force_free_resource_valid_o <= force_free_resource_valid;
free_FSM <= x"0" when state = S_IDLE else
x"1" when state = S_REQ_READ_FIFO else
x"2" when state = S_READ_FIFO else
x"3" when state = S_READ_NEXT_PAGE_ADDR else
x"4" when state = S_FREE_CURRENT_PAGE_ADDR else
x"5" when state = S_FORCE_FREE_CURRENT_PAGE_ADDR else
x"7";
wdog_o(c_FREE_FSM_IDX) <= free_FSM;
end syn;
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ af1ec690
......@@ -277,8 +277,7 @@ package swc_swcore_pkg is
pta_hp_o : out std_logic;
pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
dbg_hwdu_o : out std_logic_vector(15 downto 0);
wdog_o : out t_swc_fsms;
tap_out_o : out std_logic_vector(49+62 downto 0);
dbg_pckstart_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
......@@ -501,7 +500,6 @@ package swc_swcore_pkg is
g_mpm_partial_select_width : integer ;
g_mpm_fetch_next_pg_in_advance : boolean := false;
g_mmu_resource_num_width : integer;
g_hwdu_output_block_width : integer :=8;
g_wb_data_width : integer ;
g_wb_addr_width : integer ;
g_wb_sel_width : integer ;
......@@ -533,10 +531,8 @@ package swc_swcore_pkg is
ots_output_drop_at_rx_hp_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
dbg_hwdu_o : out std_logic_vector(g_hwdu_output_block_width -1 downto 0);
tap_out_o : out std_logic_vector(15 downto 0)
);
wdog_o : out t_swc_fsms;
tap_out_o : out std_logic_vector(15 downto 0));
end component;
component swc_multiport_pck_pg_free_module is
......@@ -578,7 +574,9 @@ component swc_multiport_pck_pg_free_module is
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_force_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
mmu_force_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0)
mmu_force_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
wdog_o : out t_swc_fsms_array(g_num_ports-1 downto 0)
);
end component;
......@@ -619,7 +617,9 @@ component swc_multiport_pck_pg_free_module is
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_force_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
mmu_force_free_resource_valid_o : out std_logic
mmu_force_free_resource_valid_o : out std_logic;
wdog_o : out t_swc_fsms
);
end component;
......@@ -666,6 +666,7 @@ component swc_multiport_pck_pg_free_module is
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
nomem_o : out std_logic;
dbg_o : out std_logic_vector(g_num_dbg_vector_width -1 downto 0);
shaper_drop_at_hp_ena_i : in std_logic
......
modules/wrsw_swcore/xswc_core.vhd
View file @ af1ec690
......@@ -77,7 +77,7 @@ entity xswc_core is
g_mpm_fetch_next_pg_in_advance : boolean ;
g_drop_outqueue_head_on_full : boolean ;
g_num_global_pause : integer := 2;
g_num_dbg_vector_width : integer := 8
g_num_dbg_vector_width : integer := 32
);
port (
clk_i : in std_logic;
......@@ -124,9 +124,13 @@ entity xswc_core is
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
rtu_abort_o : out std_logic_vector(g_num_ports - 1 downto 0)
rtu_abort_o : out std_logic_vector(g_num_ports - 1 downto 0);
);
-------------------------------------------------------------------------------
-- Watchdog outputs
-------------------------------------------------------------------------------
wdog_o : out t_swc_fsms_array(g_num_ports-1 downto 0);
nomem_o : out std_logic);
end xswc_core;
architecture rtl of xswc_core is
......@@ -151,9 +155,7 @@ architecture rtl of xswc_core is
constant c_res_mmu_resource_num : integer := 3; -- (1) unknown; (2) special; (3) normal
constant c_res_mmu_resource_num_width : integer := 2;
----------------------------------------------
constant c_hwdu_input_block_width : integer := 16;
constant c_hwdu_mmu_width : integer := 10*3;
constant c_hwdu_output_block_width : integer := 8;
----------------------------------------------------------------------------------------------------
-- signals connecting >>Input Block<< with >>Memory Management Unit<<
......@@ -352,12 +354,10 @@ architecture rtl of xswc_core is
signal mmu2ib_res_almost_full : std_logic_vector(g_num_ports*c_res_mmu_resource_num -1 downto 0);
signal mmu2ib_set_usecnt_succeeded : std_logic_vector(g_num_ports -1 downto 0);
type t_hwdu_input_block_array is array(0 to g_num_ports-1) of std_logic_vector(c_hwdu_input_block_width-1 downto 0);
type t_hwdu_output_block_array is array(0 to g_num_ports-1) of std_logic_vector(c_hwdu_output_block_width-1 downto 0);
signal hwdu_input_block : t_hwdu_input_block_array;
signal hwdu_output_block : t_hwdu_output_block_array;
signal hwdu_mmu : std_logic_vector(c_hwdu_mmu_width -1 downto 0);
signal wdog_ib : t_swc_fsms_array(g_num_ports-1 downto 0);
signal wdog_ob : t_swc_fsms_array(g_num_ports-1 downto 0);
signal wdog_free : t_swc_fsms_array(g_num_ports-1 downto 0);
signal hwdu_mmu : std_logic_vector(c_hwdu_mmu_width -1 downto 0);
signal dbg_pckstart_pageaddr : std_logic_vector(g_num_ports*c_mpm_page_addr_width - 1 downto 0);
signal dbg_pckinter_pageaddr : std_logic_vector(g_num_ports*c_mpm_page_addr_width - 1 downto 0);
......@@ -377,6 +377,8 @@ architecture rtl of xswc_core is
-- TRIG2 => tap(95 downto 64),
-- TRIG3 => tap(127 downto 96));
nomem_o <= mmu_nomem;
tap <= tap_alloc & tap_ob(2);
gen_blocks : for i in 0 to g_num_ports-1 generate
......@@ -485,7 +487,7 @@ architecture rtl of xswc_core is
-- pta_pck_size_o => ib_pck_size ((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width),
-- pta_resource_o => open,
pta_hp_o => ib_hp (i),
dbg_hwdu_o => hwdu_input_block(i),
wdog_o => wdog_ib(i),
tap_out_o => tap_ib(i),
dbg_pckstart_pageaddr_o => dbg_pckstart_pageaddr((i+1)*c_mpm_page_addr_width-1 downto i*c_mpm_page_addr_width),
......@@ -562,10 +564,9 @@ architecture rtl of xswc_core is
src_i => src_i(i),
src_o => src_o(i),
dbg_hwdu_o => hwdu_output_block(i),
wdog_o => wdog_ob(i),
tap_out_o => tap_ob(i)
);
end generate gen_blocks;
OUTPUT_TRAFFIC_SHAPER: swc_output_traffic_shaper
......@@ -621,7 +622,9 @@ architecture rtl of xswc_core is
mmu_free_pgaddr_o => ppfm_free_pgaddr,
mmu_free_last_usecnt_i => mmu2ppfm_free_last_usecnt,
mmu_force_free_resource_o => ppfm2mmu_force_free_resource,
mmu_force_free_resource_valid_o => ppfm2mmu_force_free_resource_valid
mmu_force_free_resource_valid_o => ppfm2mmu_force_free_resource_valid,
wdog_o => wdog_free
);
......@@ -801,12 +804,14 @@ architecture rtl of xswc_core is
dbg_o(31 downto 0) <= "00" & hwdu_mmu;
hwdu_gen: for i in 0 to (g_num_ports-1) generate --19 ports for 18-port switch
dbg_o((i+1)*c_hwdu_input_block_width+32-1 downto
i*c_hwdu_input_block_width+32) <= hwdu_input_block(i);
dbg_o((i+1)*c_hwdu_output_block_width+(g_num_ports*c_hwdu_input_block_width)+32-1 downto
i*c_hwdu_output_block_width+(g_num_ports*c_hwdu_input_block_width)+32) <= hwdu_output_block(i);
end generate hwdu_gen;
WDOG_GEN: for I in 0 to g_num_ports-1 generate
wdog_o(I)(c_ALLOC_FSM_IDX) <= wdog_ib(I)(c_ALLOC_FSM_IDX);
wdog_o(I)(c_TRANS_FSM_IDX) <= wdog_ib(I)(c_TRANS_FSM_IDX);
wdog_o(I)(c_RCV_FSM_IDX) <= wdog_ib(I)(c_RCV_FSM_IDX);
wdog_o(I)(c_LL_FSM_IDX) <= wdog_ib(I)(c_LL_FSM_IDX);
wdog_o(I)(c_PREP_FSM_IDX) <= wdog_ib(I)(c_PREP_FSM_IDX);
wdog_o(I)(c_SEND_FSM_IDX) <= wdog_ib(I)(c_SEND_FSM_IDX);
wdog_o(I)(c_FREE_FSM_IDX) <= wdog_free(I)(c_FREE_FSM_IDX);
end generate;
end rtl;
modules/wrsw_swcore/xswc_input_block.vhd
View file @ af1ec690
......@@ -98,6 +98,7 @@ library work;
use work.swc_swcore_pkg.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
use work.wrsw_shared_types_pkg.all;
entity xswc_input_block is
generic (
......@@ -256,8 +257,7 @@ entity xswc_input_block is
pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0);
dbg_hwdu_o : out std_logic_vector(15 downto 0);
wdog_o : out t_swc_fsms;
tap_out_o: out std_logic_vector(49 + 62 downto 0);
dbg_pckstart_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
......@@ -551,7 +551,7 @@ architecture syn of xswc_input_block is
signal lw_pckstart_pg_clred : std_logic;
signal pckstart_pg_clred : std_logic;
signal alloc_FSM : std_logic_vector(2 downto 0);
signal alloc_FSM : std_logic_vector(3 downto 0);
signal trans_FSM : std_logic_vector(3 downto 0);
signal rcv_p_FSM : std_logic_vector(3 downto 0);
signal linkl_FSM : std_logic_vector(3 downto 0);
......@@ -806,7 +806,7 @@ begin --archS_PCKSTART_SET_AND_REQ
if(rst_n_i = '0') then
--========================================
s_rcv_pck <= S_IDLE;
snk_stall_force_h <= '1';
snk_stall_force_h <= '0'; --for watchdog
snk_stall_force_l <= '1';
snk_sel_d0 <= (others => '0');
page_word_cnt <= (others => '0');
......@@ -2010,7 +2010,7 @@ begin
mpm_dlast_reg <= '0';
mpm_pg_req_d0 <= '0';
--s_ll_write <= S_IDLE;
s_ll_write <= S_IDLE;
--pckstart_pageaddr_clred <= (others => '1');--make it different then the first allocated addr
--========================================
else
......@@ -2576,12 +2576,12 @@ ll_next_addr_o <= ll_entry.next_page;
ll_next_addr_valid_o <= ll_entry.next_page_valid;
ll_wr_req_o <= ll_wr_req;
alloc_FSM <= "000" when (s_page_alloc = S_IDLE) else
"001" when (s_page_alloc = S_PCKSTART_SET_USECNT) else
"010" when (s_page_alloc = S_PCKSTART_PAGE_REQ) else
"011" when (s_page_alloc = S_PCKINTER_PAGE_REQ) else
"100" when (s_page_alloc = S_PCKSTART_SET_AND_REQ) else
"101" ;
alloc_FSM <= x"0" when (s_page_alloc = S_IDLE) else
x"1" when (s_page_alloc = S_PCKSTART_SET_USECNT) else
x"2" when (s_page_alloc = S_PCKSTART_PAGE_REQ) else
x"3" when (s_page_alloc = S_PCKINTER_PAGE_REQ) else
x"4" when (s_page_alloc = S_PCKSTART_SET_AND_REQ) else
x"5" ;
trans_FSM <= x"0" when (s_transfer_pck = S_IDLE) else
x"1" when (s_transfer_pck = S_READY) else
x"2" when (s_transfer_pck = S_WAIT_RTU_VALID) else
......@@ -2611,7 +2611,10 @@ linkl_FSM <= x"0" when (s_ll_write = S_IDLE) else
x"5" when (s_ll_write = S_SOF_ON_WR) else
x"6";
dbg_hwdu_o <= rtu_rsp_valid_i & alloc_FSM & trans_FSM & rcv_p_FSM & linkl_FSM;
wdog_o(c_ALLOC_FSM_IDX) <= alloc_FSM;
wdog_o(c_TRANS_FSM_IDX) <= trans_FSM;
wdog_o(c_RCV_FSM_IDX) <= rcv_p_FSM;
wdog_o(c_LL_FSM_IDX) <= linkl_FSM;
dbg_dropped_on_res_full <= pckstart_usecnt_req and mmu_set_usecnt_done_i and (not mmu_set_usecnt_succeeded_i);
......
modules/wrsw_swcore/xswc_output_block_new.vhd
View file @ af1ec690
......@@ -59,6 +59,7 @@ use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_private_pkg.all; -- Tom
use work.ep_wbgen2_pkg.all; -- tom
use work.wrsw_shared_types_pkg.all;
entity xswc_output_block_new is
generic (
......@@ -76,7 +77,6 @@ entity xswc_output_block_new is
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_wb_sel_width : integer;
g_hwdu_output_block_width : integer := 8;
g_wb_ob_ignore_ack : boolean := true;
g_drop_outqueue_head_on_full : boolean := true
);
......@@ -133,7 +133,7 @@ entity xswc_output_block_new is
-------------------------------------------------------------------------------
-- debugging
-------------------------------------------------------------------------------
dbg_hwdu_o : out std_logic_vector(g_hwdu_output_block_width -1 downto 0);
wdog_o : out t_swc_fsms;
tap_out_o : out std_logic_vector(15 downto 0)
);
end xswc_output_block_new;
......@@ -1040,5 +1040,8 @@ begin -- behavoural
x"4" when (s_prep_to_send = S_RETRY_PREPARE) else
x"0" when (s_prep_to_send = S_RETRY_READY) else
x"6" ;
dbg_hwdu_o(7 downto 0)<= send_FSM & prep_FSM;
wdog_o(c_PREP_FSM_IDX) <= prep_FSM;
wdog_o(c_SEND_FSM_IDX) <= send_FSM;
end behavoural;
modules/wrsw_watchdog/Manifest.py
View file @ af1ec690
files = ["xwrsw_watchdog.vhd"]
files = ["xwrsw_watchdog.vhd", "wdog_wbgen2_pkg.vhd", "wdog_wishbone_slave.vhd"]
modules/wrsw_watchdog/build_wb.sh 0 → 100755
View file @ af1ec690
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wrsw_watchdog.html -V wdog_wishbone_slave.vhd --cstyle defines --lang vhdl -K ../../sim/regs/wdog_regs.vh -p wdog_wbgen2_pkg.vhd --hstyle record wrsw_watchdog.wb
modules/wrsw_watchdog/wdog_wbgen2_pkg.vhd 0 → 100644
View file @ af1ec690
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Watchdog module
---------------------------------------------------------------------------------------
-- File : wdog_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrsw_watchdog.wb
-- Created : Tue Jun 30 11:52:29 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_watchdog.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wdog_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wdog_in_registers is record
rst_cnt_i : std_logic_vector(31 downto 0);
cr_port_i : std_logic_vector(7 downto 0);
act_i : std_logic_vector(6 downto 0);
fsm_ib_alloc_i : std_logic_vector(3 downto 0);
fsm_ib_trans_i : std_logic_vector(3 downto 0);
fsm_ib_rcv_i : std_logic_vector(3 downto 0);
fsm_ib_ll_i : std_logic_vector(3 downto 0);
fsm_ob_prep_i : std_logic_vector(3 downto 0);
fsm_ob_send_i : std_logic_vector(3 downto 0);
fsm_free_i : std_logic_vector(3 downto 0);
end record;
constant c_wdog_in_registers_init_value: t_wdog_in_registers := (
rst_cnt_i => (others => '0'),
cr_port_i => (others => '0'),
act_i => (others => '0'),
fsm_ib_alloc_i => (others => '0'),
fsm_ib_trans_i => (others => '0'),
fsm_ib_rcv_i => (others => '0'),
fsm_ib_ll_i => (others => '0'),
fsm_ob_prep_i => (others => '0'),
fsm_ob_send_i => (others => '0'),
fsm_free_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_wdog_out_registers is record
cr_port_o : std_logic_vector(7 downto 0);
cr_port_load_o : std_logic;
cr_rst_o : std_logic;
end record;
constant c_wdog_out_registers_init_value: t_wdog_out_registers := (
cr_port_o => (others => '0'),
cr_port_load_o => '0',
cr_rst_o => '0'
);
function "or" (left, right: t_wdog_in_registers) return t_wdog_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body wdog_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wdog_in_registers) return t_wdog_in_registers is
variable tmp: t_wdog_in_registers;
begin
tmp.rst_cnt_i := f_x_to_zero(left.rst_cnt_i) or f_x_to_zero(right.rst_cnt_i);
tmp.cr_port_i := f_x_to_zero(left.cr_port_i) or f_x_to_zero(right.cr_port_i);
tmp.act_i := f_x_to_zero(left.act_i) or f_x_to_zero(right.act_i);
tmp.fsm_ib_alloc_i := f_x_to_zero(left.fsm_ib_alloc_i) or f_x_to_zero(right.fsm_ib_alloc_i);
tmp.fsm_ib_trans_i := f_x_to_zero(left.fsm_ib_trans_i) or f_x_to_zero(right.fsm_ib_trans_i);
tmp.fsm_ib_rcv_i := f_x_to_zero(left.fsm_ib_rcv_i) or f_x_to_zero(right.fsm_ib_rcv_i);
tmp.fsm_ib_ll_i := f_x_to_zero(left.fsm_ib_ll_i) or f_x_to_zero(right.fsm_ib_ll_i);
tmp.fsm_ob_prep_i := f_x_to_zero(left.fsm_ob_prep_i) or f_x_to_zero(right.fsm_ob_prep_i);
tmp.fsm_ob_send_i := f_x_to_zero(left.fsm_ob_send_i) or f_x_to_zero(right.fsm_ob_send_i);
tmp.fsm_free_i := f_x_to_zero(left.fsm_free_i) or f_x_to_zero(right.fsm_free_i);
return tmp;
end function;
end package body;
modules/wrsw_watchdog/wdog_wishbone_slave.vhd 0 → 100644
View file @ af1ec690
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Watchdog module
---------------------------------------------------------------------------------------
-- File : wdog_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wrsw_watchdog.wb
-- Created : Tue Jun 30 11:52:29 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_watchdog.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wdog_wbgen2_pkg.all;
entity wdog_wishbone_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_wdog_in_registers;
regs_o : out t_wdog_out_registers
);
end wdog_wishbone_slave;
architecture syn of wdog_wishbone_slave is
signal wdog_cr_rst_dly0 : std_logic ;
signal wdog_cr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
regs_o.cr_port_load_o <= '0';
wdog_cr_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.cr_port_load_o <= '0';
wdog_cr_rst_int <= '0';
ack_in_progress <= '0';
else
regs_o.cr_port_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rst_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
regs_o.cr_port_load_o <= '1';
wdog_cr_rst_int <= wrdata_reg(31);
end if;
rddata_reg(7 downto 0) <= regs_i.cr_port_i;
rddata_reg(31) <= '0';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(6 downto 0) <= regs_i.act_i;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.fsm_ib_alloc_i;
rddata_reg(7 downto 4) <= regs_i.fsm_ib_trans_i;
rddata_reg(11 downto 8) <= regs_i.fsm_ib_rcv_i;
rddata_reg(15 downto 12) <= regs_i.fsm_ib_ll_i;
rddata_reg(19 downto 16) <= regs_i.fsm_ob_prep_i;
rddata_reg(23 downto 20) <= regs_i.fsm_ob_send_i;
rddata_reg(27 downto 24) <= regs_i.fsm_free_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- counter value
-- Port select
regs_o.cr_port_o <= wrdata_reg(7 downto 0);
-- Force reset
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
wdog_cr_rst_dly0 <= '0';
regs_o.cr_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
wdog_cr_rst_dly0 <= wdog_cr_rst_int;
regs_o.cr_rst_o <= wdog_cr_rst_int and (not wdog_cr_rst_dly0);
end if;
end process;
-- bit-per-fsm activity since the last readout
-- IB alloc FSM state
-- IB transfer FSM state
-- IB receive FSM state
-- IB LL FSM state
-- OB prepare FSM state
-- OB send FSM state
-- FREE FSM state
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/wrsw_watchdog/wrsw_watchdog.wb 0 → 100644
View file @ af1ec690
-- -*- Mode: LUA; tab-width: 2 -*-
-- White-Rabbit Watchdog Module
-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
--
-- Use wbgen2 to generate code, documentation and more.
-- wbgen2 is available at:
-- http://www.ohwr.org/projects/wishbone-gen
--
peripheral {
name = "WR Watchdog module";
description = "The module monitors the Switching Core and performs a reset when swcore is stuck";
hdl_entity = "wdog_wishbone_slave";
prefix = "wdog";
reg {
name = "Restart counter";
description = "Counts how many times watchdog had to restart the swcore";
prefix = "RST_CNT";
field {
name = "counter value";
size = 32;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Port select";
prefix = "PORT";
size = 8;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Force reset";
prefix = "RST";
size = 1;
align = 31;
type = MONOSTABLE;
access_dev = READ_ONLY;
access_bus = WRITE_ONLY;
};
};
reg {
name = "Port FSM activity register";
prefix = "ACT";
field {
name = "bit-per-fsm activity since the last readout";
size = 7;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Port FSM register";
prefix = "FSM";
field {
name = "IB alloc FSM state";
prefix = "IB_ALLOC";
size = 4;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "IB transfer FSM state";
prefix = "IB_TRANS";
size = 4;
align = 4;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "IB receive FSM state";
prefix = "IB_RCV";
size = 4;
align = 8;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "IB LL FSM state";
prefix = "IB_LL";
size = 4;
align = 12;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "OB prepare FSM state";
prefix = "OB_PREP";
size = 4;
align = 16;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "OB send FSM state";
prefix = "OB_SEND";
size = 4;
align = 20;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "FREE FSM state";
prefix = "FREE";
size = 4;
align = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
};
modules/wrsw_watchdog/xwrsw_watchdog.vhd
View file @ af1ec690
......@@ -3,18 +3,21 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wr_fabric_pkg.all;
use work.wishbone_pkg.all;
use work.wrsw_shared_types_pkg.all;
use work.wdog_wbgen2_pkg.all;
entity xwrsw_watchdog is
generic(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_num_ports : integer := 18);
port(
rst_n_i : in std_logic;
clk_i : in std_logic;
force_rst_i : in std_logic;
swc_nomem_i : in std_logic;
-- statistics to be exported by HWIU
restart_cnt_o : out std_logic_vector(31 downto 0);
swc_fsms_i : in t_swc_fsms_array(g_num_ports-1 downto 0);
swcrst_n_o : out std_logic;
epstop_o : out std_logic;
......@@ -25,13 +28,47 @@ entity xwrsw_watchdog is
snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0));
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end xwrsw_watchdog;
architecture behav of xwrsw_watchdog is
component wdog_wishbone_slave
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_wdog_in_registers;
regs_o : out t_wdog_out_registers
);
end component;
type t_act_array is array(integer range <>) of std_logic_vector(6 downto 0);
constant c_RST_TIME : integer := 128;
constant c_SWCRST_TIME : integer := 8;
constant c_NOMEM_THR : integer := 10000; --62500000;
constant c_SWC_FSMS_ZERO : t_swc_fsms :=
(x"0", x"0", x"0", x"0", x"0", x"0", x"0");
signal wb_regs_in : t_wdog_in_registers;
signal wb_regs_out : t_wdog_out_registers;
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal sel_port : integer range 0 to g_num_ports-1;
signal fsm_act : t_act_array(g_num_ports-1 downto 0);
signal fsm_act_frozen : t_act_array(g_num_ports-1 downto 0);
signal nomem_cnt : unsigned(25 downto 0);
signal nomem_trig : std_logic;
......@@ -40,8 +77,97 @@ architecture behav of xwrsw_watchdog is
signal rst_trig : std_logic;
signal rst_trig_d0 : std_logic;
signal reset_mode : std_logic;
signal swc_fsms_prev : t_swc_fsms_array(g_num_ports-1 downto 0);
begin
-- Standard Wishbone stuff
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => true,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
slave_i => wb_i,
slave_o => wb_o,
master_i => wb_out,
master_o => wb_in);
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.int <= '0';
U_WB_Slave : wdog_wishbone_slave
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_in.adr(1 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o=> wb_out.stall,
regs_i => wb_regs_in,
regs_o => wb_regs_out);
--------------------------
wb_regs_in.rst_cnt_i <= std_logic_vector(watchdog_cnt);
process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i='0') then
sel_port <= 0;
elsif(wb_regs_out.cr_port_load_o='1') then
sel_port <= to_integer(unsigned(wb_regs_out.cr_port_o));
end if;
end if;
end process;
wb_regs_in.cr_port_i <= std_logic_vector(to_unsigned(sel_port, 8));
-- FSM export for software watchdog
GEN_PORT_EXPORT: for I in 0 to g_num_ports-1 generate
process(clk_i)
variable fidx : integer range 0 to 6;
begin
if rising_edge(clk_i) then
if(rst_n_i='0') then
swc_fsms_prev(I) <= c_SWC_FSMS_ZERO;
fsm_act(I) <= (others=>'0');
fsm_act_frozen(I) <= (others=>'0');
else
for fidx in 0 to 6 loop
if(swc_fsms_i(I)(fidx) /= swc_fsms_prev(I)(fidx)) then
fsm_act(I)(fidx) <= '1';
end if;
end loop;
if(wb_regs_out.cr_port_load_o='1' and
wb_regs_out.cr_port_o = std_logic_vector(to_unsigned(I, 8))) then
swc_fsms_prev(I) <= swc_fsms_i(I);
fsm_act_frozen(I) <= fsm_act(I);
fsm_act(I) <= (others=>'0');
end if;
end if;
end if;
end process;
end generate;
wb_regs_in.fsm_ib_alloc_i <= swc_fsms_i(sel_port)(c_ALLOC_FSM_IDX);
wb_regs_in.fsm_ib_trans_i <= swc_fsms_i(sel_port)(c_TRANS_FSM_IDX);
wb_regs_in.fsm_ib_rcv_i <= swc_fsms_i(sel_port)(c_RCV_FSM_IDX);
wb_regs_in.fsm_ib_ll_i <= swc_fsms_i(sel_port)(c_LL_FSM_IDX);
wb_regs_in.fsm_ob_prep_i <= swc_fsms_i(sel_port)(c_PREP_FSM_IDX);
wb_regs_in.fsm_ob_send_i <= swc_fsms_i(sel_port)(c_SEND_FSM_IDX);
wb_regs_in.fsm_free_i <= swc_fsms_i(sel_port)(c_FREE_FSM_IDX);
wb_regs_in.act_i <= fsm_act_frozen(sel_port);
-- Hanging detection
process(clk_i)
begin
......@@ -59,7 +185,7 @@ begin
end if;
end process;
rst_trig <= force_rst_i or nomem_trig;
rst_trig <= wb_regs_out.cr_rst_o or nomem_trig;
-- Resetting SwCore and Endpoints
process(clk_i)
......@@ -87,7 +213,6 @@ begin
end if;
end if;
end process;
restart_cnt_o <= std_logic_vector(watchdog_cnt);
-- switching core we reset only for one clk cycle
swcrst_n_o <= '0' when(reset_mode='1' and rst_cnt < c_SWCRST_TIME) else
......
top/bare_top/scb_top_bare.vhd
View file @ af1ec690
......@@ -187,19 +187,17 @@ end scb_top_bare;
architecture rtl of scb_top_bare is
constant c_GW_VERSION : std_logic_vector(31 downto 0) := x"20_02_14_00"; --DD_MM_YY_VV
constant c_NUM_WB_SLAVES : integer := 13;
constant c_NUM_WB_SLAVES : integer := 14;
constant c_NUM_PORTS : integer := g_num_ports;
constant c_MAX_PORTS : integer := 18;
constant c_NUM_GL_PAUSE : integer := 2; -- number of output global PAUSE sources for SWcore
constant c_RTU_EVENTS : integer := 9; -- number of RMON events per port
constant c_DBG_V_SWCORE : integer := (3*10) + 2 + -- 3 resources, each has with of CNT of 10 bits +2 to make it 32
(g_num_ports+1)*16 + -- states of input blocks (including NIC)
(g_num_ports+1)*8; -- states of output blocks (including NIC)
constant c_DBG_V_SWCORE : integer := (3*10) + 2; -- 3 resources, each has with of CNT of 10 bits +2 to make it 32
constant c_DBG_N_REGS : integer := 1 + integer(ceil(real(c_DBG_V_SWCORE)/real(32))); -- 32-bits debug registers which go to HWIU
constant c_TRU_EVENTS : integer := 1;
constant c_ALL_EVENTS : integer := c_TRU_EVENTS + c_RTU_EVENTS + c_epevents_sz;
constant c_DUMMY_RMON : boolean := false; -- define TRUE to enable dummy_rmon module for debugging PSTAT
constant c_NUM_GPIO_PINS : integer := 2;
constant c_NUM_GPIO_PINS : integer := 1;
constant c_NUM_IRQS : integer := 4;
-- constant c_epevents_sz : integer := 15;
-------------------------------------------------------------------------------
......@@ -219,6 +217,7 @@ architecture rtl of scb_top_bare is
constant c_SLAVE_TATSU : integer := 10;
constant c_SLAVE_PSTATS : integer := 11;
constant c_SLAVE_HWIU : integer := 12;
constant c_SLAVE_WDOG : integer := 13;
--constant c_SLAVE_DUMMY : integer := 13;
......@@ -321,6 +320,8 @@ architecture rtl of scb_top_bare is
signal link_kill : std_logic_vector(c_NUM_PORTS-1 downto 0);
signal rst_n_swc : std_logic;
signal swc_nomem : std_logic;
signal swc_wdog_out : t_swc_fsms_array(c_NUM_PORTS downto 0);
signal ep_stop_traffic : std_logic;
......@@ -829,7 +830,8 @@ begin
rtu_rsp_i => rtu_rsp,
rtu_ack_o => swc_rtu_ack,
rtu_abort_o =>rtu_rsp_abort-- open --rtu_rsp_abort
rtu_abort_o =>rtu_rsp_abort,-- open --rtu_rsp_abort
wdog_o => swc_wdog_out
);
-- SWcore global pause nr=0 assigned to TRU
......@@ -1131,11 +1133,9 @@ begin
port map(
rst_n_i => rst_n_periph,
clk_i => clk_sys,
force_rst_i => gpio_out(1),
swc_nomem_i => swc_nomem,
swc_fsms_i => swc_wdog_out,
restart_cnt_o => open,
swcrst_n_o => rst_n_swc,
epstop_o => ep_stop_traffic,
......@@ -1145,7 +1145,9 @@ begin
snk_i => wrfreg_src_out,
snk_o => wrfreg_src_in,
src_o => swc_snk_in,
src_i => swc_snk_out);
src_i => swc_snk_out,
wb_i => cnx_master_out(c_SLAVE_WDOG),
wb_o => cnx_master_in(c_SLAVE_WDOG));
end generate;
GEN_NO_SWC_RST: if(not g_with_watchdog) generate
......
top/bare_top/wrs_sdb_pkg.vhd
View file @ af1ec690
......@@ -204,6 +204,22 @@ package wrs_sdb_pkg is
date => x"20141120",
name => "WRSW GEN 10MHz ")));
constant c_xwrsw_watchdog_sdb: t_sdb_device := (
abi_class => x"0000",
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7",
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"d1dedca6", -- echo -n "xwrsw_watchdog" | md5sum - | cut -c1-8
version => x"00000001",
date => x"20150630",
name => "WRSW WATCHDOG ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
......@@ -243,7 +259,7 @@ package wrs_sdb_pkg is
f_xwb_bridge_layout_sdb(true, c_epbar_layout, c_epbar_sdb_address);
-- WRS main crossbar
constant c_layout : t_sdb_record_array(12+4 downto 0) :=
constant c_layout : t_sdb_record_array(13+4 downto 0) :=
(0 => f_sdb_embed_bridge(c_rtbar_bridge_sdb, x"00000000"), --RT subsystem
1 => f_sdb_embed_device(c_xwrsw_nic_sdb, x"00020000"), --NIC
2 => f_sdb_embed_bridge(c_epbar_bridge_sdb, x"00030000"), --Endpoints
......@@ -257,10 +273,11 @@ package wrs_sdb_pkg is
10 => f_sdb_embed_device(c_xwrsw_tatsu_sdb, x"00057000"), --TATSU
11 => f_sdb_embed_device(c_xwrsw_pstats_sdb, x"00058000"), --PSTATS
12 => f_sdb_embed_device(c_xwrsw_hwiu_sdb, x"00059000"), --HWIU
13 => f_sdb_embed_repo_url(c_sdb_repo_url),
14 => f_sdb_embed_synthesis(c_sdb_top_syn_info),
15 => f_sdb_embed_synthesis(c_sdb_general_cores_syn_info),
16 => f_sdb_embed_synthesis(c_sdb_wr_cores_syn_info));
13 => f_sdb_embed_device(c_xwrsw_watchdog_sdb, x"0005a000"), --Watchdog
14 => f_sdb_embed_repo_url(c_sdb_repo_url),
15 => f_sdb_embed_synthesis(c_sdb_top_syn_info),
16 => f_sdb_embed_synthesis(c_sdb_general_cores_syn_info),
17 => f_sdb_embed_synthesis(c_sdb_wr_cores_syn_info));
constant c_sdb_address : t_wishbone_address := x"00070000";
end wrs_sdb_pkg;
top/bare_top/wrsw_components_pkg.vhd
View file @ af1ec690
......@@ -279,7 +279,7 @@ package wrsw_components_pkg is
g_mpm_fetch_next_pg_in_advance : boolean ;
g_drop_outqueue_head_on_full : boolean ;
g_num_global_pause : integer ;
g_num_dbg_vector_width : integer := 8
g_num_dbg_vector_width : integer := 32
);
port (
clk_i : in std_logic;
......@@ -295,10 +295,11 @@ package wrsw_components_pkg is
global_pause_i : in t_global_pause_request_array(g_num_global_pause-1 downto 0);
perport_pause_i : in t_pause_request_array(g_num_ports-1 downto 0);
shaper_drop_at_hp_ena_i : in std_logic := '0';
dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0);
dbg_o : out std_logic_vector(g_num_dbg_vector_width - 1 downto 0);
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
rtu_abort_o : out std_logic_vector(g_num_ports - 1 downto 0);
wdog_o : out t_swc_fsms_array(g_num_ports-1 downto 0);
nomem_o : out std_logc
);
end component;
......@@ -395,13 +396,14 @@ package wrsw_components_pkg is
component xwrsw_watchdog
generic(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_num_ports : integer := 18);
port(
rst_n_i : in std_logic;
clk_i : in std_logic;
force_rst_i : in std_logic;
swc_nomem_i : in std_logic;
restart_cnt_o : out std_logic_vector(31 downto 0);
swc_fsms_i : in t_swc_fsms_array(g_num_ports-1 downto 0);
swcrst_n_o : out std_logic;
epstop_o : out std_logic;
rtu_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
......@@ -409,7 +411,9 @@ package wrsw_components_pkg is
snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0));
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
--TEMP
......
top/bare_top/wrsw_top_pkg.vhd
View file @ af1ec690
......@@ -336,7 +336,7 @@ package wrsw_top_pkg is
g_mpm_fetch_next_pg_in_advance : boolean ;
g_drop_outqueue_head_on_full : boolean ;
g_num_global_pause : integer ;
g_num_dbg_vector_width : integer := 8
g_num_dbg_vector_width : integer := 32
);
port (
clk_i : in std_logic;
......@@ -356,6 +356,7 @@ package wrsw_top_pkg is
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0);
rtu_abort_o : out std_logic_vector(g_num_ports - 1 downto 0);
wdog_o : out t_swc_fsms_array(g_num_ports-1 downto 0);
nomem_o : out std_logic
);
end component;
......@@ -440,13 +441,14 @@ package wrsw_top_pkg is
component xwrsw_watchdog
generic(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_num_ports : integer := 18);
port(
rst_n_i : in std_logic;
clk_i : in std_logic;
force_rst_i : in std_logic;
swc_nomem_i : in std_logic;
restart_cnt_o : out std_logic_vector(31 downto 0);
swc_fsms_i : in t_swc_fsms_array(g_num_ports-1 downto 0);
swcrst_n_o : out std_logic;
epstop_o : out std_logic;
rtu_ack_i : in std_logic_vector(g_num_ports-1 downto 0);
......@@ -454,7 +456,9 @@ package wrsw_top_pkg is
snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0));
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
component xwrsw_hwdu
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment