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White Rabbit Switch - Gateware
Commit b2a62adf authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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10mhz_out: adding iodelay to pps_out and wb register to control it

parent db955485
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wr-cores @ 86df7f9c
Subproject commit a9cf9115e07f9707c1653ee4a6d2e0afb3f179ce
Subproject commit 86df7f9ccec063ab4f88baca1a53332f2e7d0571
modules/wrsw_rt_subsystem/gen10_wbgen2_pkg.vhd
View file @ b2a62adf
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : gen10_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrsw_gen_10mhz.wb
-- Created : Wed Dec 3 17:27:21 2014
-- Created : Tue Dec 9 10:20:16 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_gen_10mhz.wb
......@@ -22,11 +22,13 @@ package gen10_wbgen2_pkg is
type t_gen10_in_registers is record
ior_tap_cur_i : std_logic_vector(4 downto 0);
ior_lck_i : std_logic;
pps_ior_tap_cur_i : std_logic_vector(4 downto 0);
end record;
constant c_gen10_in_registers_init_value: t_gen10_in_registers := (
ior_tap_cur_i => (others => '0'),
ior_lck_i => '0'
ior_lck_i => '0',
pps_ior_tap_cur_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -40,6 +42,8 @@ package gen10_wbgen2_pkg is
csr_wr_o : std_logic;
ior_tap_set_o : std_logic_vector(4 downto 0);
ior_tap_set_wr_o : std_logic;
pps_ior_tap_set_o : std_logic_vector(4 downto 0);
pps_ior_tap_set_wr_o : std_logic;
end record;
constant c_gen10_out_registers_init_value: t_gen10_out_registers := (
......@@ -50,7 +54,9 @@ package gen10_wbgen2_pkg is
csr_o => (others => '0'),
csr_wr_o => '0',
ior_tap_set_o => (others => '0'),
ior_tap_set_wr_o => '0'
ior_tap_set_wr_o => '0',
pps_ior_tap_set_o => (others => '0'),
pps_ior_tap_set_wr_o => '0'
);
function "or" (left, right: t_gen10_in_registers) return t_gen10_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -83,6 +89,7 @@ variable tmp: t_gen10_in_registers;
begin
tmp.ior_tap_cur_i := f_x_to_zero(left.ior_tap_cur_i) or f_x_to_zero(right.ior_tap_cur_i);
tmp.ior_lck_i := f_x_to_zero(left.ior_lck_i) or f_x_to_zero(right.ior_lck_i);
tmp.pps_ior_tap_cur_i := f_x_to_zero(left.pps_ior_tap_cur_i) or f_x_to_zero(right.pps_ior_tap_cur_i);
return tmp;
end function;
end package body;
modules/wrsw_rt_subsystem/gen10_wishbone_slave.vhd
View file @ b2a62adf
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : gen10_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wrsw_gen_10mhz.wb
-- Created : Wed Dec 3 17:27:21 2014
-- Created : Tue Dec 9 10:20:16 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_gen_10mhz.wb
......@@ -21,7 +21,7 @@ entity gen10_wishbone_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -41,7 +41,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -68,6 +68,7 @@ begin
regs_o.dcr_low_width_wr_o <= '0';
regs_o.csr_wr_o <= '0';
regs_o.ior_tap_set_wr_o <= '0';
regs_o.pps_ior_tap_set_wr_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -78,17 +79,19 @@ begin
regs_o.dcr_low_width_wr_o <= '0';
regs_o.csr_wr_o <= '0';
regs_o.ior_tap_set_wr_o <= '0';
regs_o.pps_ior_tap_set_wr_o <= '0';
ack_in_progress <= '0';
else
regs_o.pr_hp_width_wr_o <= '0';
regs_o.dcr_low_width_wr_o <= '0';
regs_o.csr_wr_o <= '0';
regs_o.ior_tap_set_wr_o <= '0';
regs_o.pps_ior_tap_set_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
regs_o.pr_hp_width_wr_o <= '1';
end if;
......@@ -126,7 +129,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
when "001" =>
if (wb_we_i = '1') then
regs_o.dcr_low_width_wr_o <= '1';
end if;
......@@ -164,7 +167,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
when "010" =>
if (wb_we_i = '1') then
regs_o.csr_wr_o <= '1';
end if;
......@@ -202,7 +205,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
when "011" =>
if (wb_we_i = '1') then
regs_o.ior_tap_set_wr_o <= '1';
end if;
......@@ -236,6 +239,40 @@ begin
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
regs_o.pps_ior_tap_set_wr_o <= '1';
end if;
rddata_reg(12 downto 8) <= regs_i.pps_ior_tap_cur_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -263,6 +300,10 @@ begin
regs_o.ior_tap_set_o <= wrdata_reg(4 downto 0);
-- Current delay value read from IODelay
-- IOdelay locked
-- Required delay value
-- pass-through field: Required delay value in register: PPS IODelay Register
regs_o.pps_ior_tap_set_o <= wrdata_reg(4 downto 0);
-- Current delay value read from IODelay
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wrsw_rt_subsystem/wrsw_gen_10mhz.wb
View file @ b2a62adf
......@@ -99,4 +99,30 @@ this problem.";
};
};
reg {
name = "PPS IODelay Register";
description = "Used to control IODelay attached to 1-PPS signal generated \
from the switch. It can be used to preciesly align 1-PPS with CLK2 out.";
prefix = "PPS_IOR";
field {
name = "Required delay value";
prefix = "TAP_SET";
size = 5;
type = PASS_THROUGH;
access_dev = READ_ONLY;
access_bus = WRITE_ONLY;
};
field {
name = "Current delay value read from IODelay";
prefix = "TAP_CUR";
align = 8;
size = 5;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
}
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ b2a62adf
......@@ -99,6 +99,12 @@ entity wrsw_rt_subsystem is
sel_clk_sys_o : out std_logic; -- system clock selection: 0 = startup
-- clock, 1 = PLL clock
-- Wired to IODelay in the top module for precise 1-PPS out alignment
-- with clk_aux
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
-- WR timebase
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
......@@ -192,6 +198,9 @@ architecture rtl of wrsw_rt_subsystem is
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0);
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end component;
......@@ -444,6 +453,9 @@ begin -- rtl
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
ppsdel_tap_i => ppsdel_tap_i,
ppsdel_tap_o => ppsdel_tap_o,
ppsdel_tap_wr_o => ppsdel_tap_wr_o,
slave_i => cnx_master_out(c_SLAVE_GEN10),
slave_o => cnx_master_in(c_SLAVE_GEN10));
......
modules/wrsw_rt_subsystem/xwrsw_gen_10mhz.vhd
View file @ b2a62adf
......@@ -62,6 +62,12 @@ entity xwrsw_gen_10mhz is
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- can be wired to IODelay component in top module for precise 1-PPS
-- alignment with clk_aux
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out);
attribute maxdelay : string;
......@@ -74,7 +80,7 @@ architecture behav of xwrsw_gen_10mhz is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -167,7 +173,7 @@ begin
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_in.adr(1 downto 0),
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
......@@ -179,6 +185,11 @@ begin
regs_i => wb_regs_in,
regs_o => wb_regs_out);
wb_regs_in.pps_ior_tap_cur_i <= ppsdel_tap_i;
ppsdel_tap_o <= wb_regs_out.pps_ior_tap_set_o;
ppsdel_tap_wr_o <= wb_regs_out.pps_ior_tap_set_wr_o;
process(clk_i)
begin
if rising_edge(clk_i) then
......
top/bare_top/scb_top_bare.vhd
View file @ b2a62adf
......@@ -387,6 +387,10 @@ architecture rtl of scb_top_bare is
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal pps_o_predelay : std_logic;
signal ppsdel_tap_out : std_logic_vector(4 downto 0);
signal ppsdel_tap_in : std_logic_vector(4 downto 0);
signal ppsdel_tap_wr_in : std_logic;
signal shaper_request : t_global_pause_request;
signal shaper_drop_at_hp_ena : std_logic;
signal fc_rx_pause : t_pause_request_array(g_num_ports+1-1 downto 0);
......@@ -520,10 +524,14 @@ begin
pps_csync_o => pps_csync,
pps_valid_o => pps_valid,
pps_ext_i => pps_i,
pps_ext_o => pps_o,
pps_ext_o => pps_o_predelay,
sel_clk_sys_o => sel_clk_sys,
ppsdel_tap_i => ppsdel_tap_out,
ppsdel_tap_o => ppsdel_tap_in,
ppsdel_tap_wr_o => ppsdel_tap_wr_in,
tm_utc_o => tm_utc,
tm_cycles_o => tm_cycles,
tm_time_valid_o => tm_time_valid,
......@@ -537,6 +545,32 @@ begin
pll_reset_n_o => pll_reset_n_o,
spll_dbg_o => spll_dbg_o);
U_DELAY_PPS: IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "VAR_LOADABLE",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA")
port map (
DATAOUT => pps_o,
DATAIN => '0',
C => clk_sys,
CE => '0',
INC => '0',
IDATAIN => '0',
ODATAIN => pps_o_predelay,
RST => ppsdel_tap_wr_in,
T => '0',
CNTVALUEIN => ppsdel_tap_in,
CNTVALUEOUT => ppsdel_tap_out,
CLKIN => '0',
CINVCTRL => '0');
U_IRQ_Controller : xwb_vic
generic map (
g_interface_mode => PIPELINED,
......
top/bare_top/wrsw_components_pkg.vhd
View file @ b2a62adf
......@@ -223,6 +223,9 @@ package wrsw_components_pkg is
pps_p_o : out std_logic;
pps_raw_i : in std_logic;
sel_clk_sys_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ b2a62adf
......@@ -227,6 +227,9 @@ package wrsw_top_pkg is
pps_ext_i : in std_logic;
pps_ext_o : out std_logic;
sel_clk_sys_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
......
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