adding missing clk_ext_mul_locked_i so that the simulation does not complain

b7960025 · Grzegorz Daniluk · fba090a1 · b7960025 · b7960025
Commit b7960025 authored Oct 30, 2015 by Grzegorz Daniluk
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scb_top_sim.vhd top/bare_top/scb_top_sim.vhd +1 -0

wrsw_top_pkg.vhd top/bare_top/wrsw_top_pkg.vhd +1 -0

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--- a/top/bare_top/scb_top_sim.vhd
+++ b/top/bare_top/scb_top_sim.vhd
@@ -190,6 +190,7 @@ begin  -- rtl
 --      clk_sys_i           => clk_sys_i,
      clk_aux_i           => clk_aux_i,
      clk_ext_mul_i       => '0',
+      clk_ext_mul_locked_i=> '1',
      cpu_wb_i            => cpu_wb_in,
      cpu_wb_o            => cpu_wb_out,
      cpu_irq_n_o         => cpu_irq_n,

--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
@@ -281,6 +281,7 @@ package wrsw_top_pkg is
      clk_dmtd_i          : in  std_logic;
      clk_aux_i           : in  std_logic;
      clk_ext_mul_i       : in  std_logic;
+		  clk_ext_mul_locked_i:	in std_logic;
      clk_sys_o           : out std_logic;
      cpu_wb_i            : in  t_wishbone_slave_in;
      cpu_wb_o            : out t_wishbone_slave_out;