[testbench+EP] added simulation of hw-based generation of test frames in EP

b8ce9f54 · Maciej Lipinski · ead28df0 · f6bed246 · b8ce9f54 · b8ce9f54
Commit b8ce9f54 authored Jan 29, 2014 by Maciej Lipinski
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wr-cores ip_cores/wr-cores +1 -1

simdrv_wr_endpoint.svh testbench/scb_top/simdrv_wr_endpoint.svh +62 -0

main.sv testbench/swcore/allocator/main.sv +1 -0

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--- a/wr-cores @ f6bed246
+++ b/wr-cores @ f6bed246
-Subproject commit 9b98461623871b2d3d5691b6d948af96cd51f009
+Subproject commit f6bed2462d3f6b8beb937ca545cd8ee45b932161
--- a/testbench/scb_top/simdrv_wr_endpoint.svh
+++ b/testbench/scb_top/simdrv_wr_endpoint.svh
@@ -54,7 +54,14 @@ class CSimDrv_WR_Endpoint;

      if(data.size() & 1)
        $fatal("CSimDrv_WR_Endpoint::write_template(): data size must be even");
+      
+      if(user_offset >= data.size()-2)
+        $fatal("CSimDrv_WR_Endpoint::write_template(): user_offset cannot be set to the last word of the template");
+
+      if(user_offset & 1)
+        $fatal("CSimDrv_WR_Endpoint::write_template(): user_offset must be even");

+     
      $display("write_template: size %d", data.size());
      
      for(i=0;i<data.size();i+=2)
@@ -74,6 +81,41 @@ class CSimDrv_WR_Endpoint;
        end
   endtask // write_template

+   task write_inj_gen_frame(byte header[], int frame_size);
+      int i;
+      int slot = 0;
+
+      if(header.size() & 1)
+        $fatal("CSimDrv_WR_Endpoint::write_inj_gen_frame(): header size must be even");
+      if(frame_size < 64)
+        $fatal("CSimDrv_WR_Endpoint::write_inj_gen_frame(): frame size needs to be greater than 64");
+
+      $display("write_template: size %d",frame_size);
+      
+      frame_size = frame_size -4;//CRC which is automaticly suffixed
+      for(i=0;i<frame_size;i+=2)
+        begin
+           uint64_t v = 0; 
+           if(i < header.size())
+             v = ((header[i] << 8) | header[i+1]) & 64'h0000FFFF;
+           else
+             v = 0;
+           
+           if(i == 0)
+             v |= (1<<16); // start of template
+
+           if((frame_size & 1) && (i == (frame_size - 1))) // end of template with odd size
+             v |= (1<<16) | (1<<17);
+           else if(i == (frame_size - 2)) // end of template with even size
+             v |= (1<<16);
+           
+           if(i == header.size())
+             v |= (1<<17); // place for frame ID
+
+           vcr1_buffer_write(0, slot * 64 + i/2, v);
+        end
+   endtask // write_template
+
   task pfilter_load_microcode(uint64_t mcode[]);
      int i;

@@ -171,6 +213,26 @@ class CSimDrv_WR_Endpoint;
              txpause_802_3, rxpause_802_3, txpause_802_1q, rxpause_802_1q);     
   endtask // automatic

+   task automatic inject_gen_ctrl_config(int interframe_gap, int sel_id);
+     uint64_t wval = 0;
+     wval  = (interframe_gap << `EP_INJ_CTRL_PIC_CONF_IFG_OFFSET) & `EP_INJ_CTRL_PIC_CONF_IFG | 
+             (sel_id         << `EP_INJ_CTRL_PIC_CONF_SEL_OFFSET) & `EP_INJ_CTRL_PIC_CONF_SEL |
+              `EP_INJ_CTRL_PIC_VALID;
+     m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+     $display("INJ ctrl cofig: interframe gap=%1d, pattern sel id=%1d",interframe_gap,sel_id);     
+   endtask // automatic
+   task automatic inject_gen_ctrl_enable();
+     uint64_t wval = 0;
+     wval  = `EP_INJ_CTRL_PIC_ENA;
+     m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+     $display("INJ ctrl cofig: enabled");     
+   endtask // automatic
+   task automatic inject_gen_ctrl_disable();
+     uint64_t wval = 0;
+     m_acc.write(m_base + `ADDR_EP_INJ_CTRL, wval);
+     $display("INJ ctrl cofig: disabled");     
+   endtask // automatic
+

 endclass // CSimDrv_WR_Endpoint


--- a/testbench/swcore/allocator/main.sv
+++ b/testbench/swcore/allocator/main.sv
@@ -14,6 +14,7 @@ typedef struct {
   int         page;
 } alloc_request_t;

+
 function automatic int first_free(int tab[]);
   int         i;