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White Rabbit Switch - Gateware
Commits
bd2d43d2
Commit
bd2d43d2
authored
Aug 16, 2013
by
Grzegorz Daniluk
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module_resource_test: endpoint optimization
parent
27c0d6db
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4 changed files
with
41 additions
and
6 deletions
+41
-6
wr-cores
ip_cores/wr-cores
+1
-1
module_test_top_bare.vhd
top/module_test/module_test_top_bare.vhd
+14
-0
scb_top_synthesis.vhd
top/module_test/scb_top_synthesis.vhd
+1
-1
test_top_pkg.vhd
top/module_test/test_top_pkg.vhd
+25
-4
No files found.
wr-cores
@
4a2807c8
Subproject commit
b5d79e6f0a3ca997c3185bc564b4ccb15f3f9fcd
Subproject commit
4a2807c8c04ea3ad1ff401389687093a62d0dc0a
top/module_test/module_test_top_bare.vhd
View file @
bd2d43d2
...
...
@@ -138,6 +138,20 @@ begin
);
end
generate
;
GEN_Endpoint
:
if
g_module_name
=
"Endpnt"
generate
DUT_EP
:
endpoint_vectorized_top
generic
map
(
g_in_bits
=>
f_invec_len
(
"Endpnt"
),
g_out_bits
=>
f_outvec_len
(
"Endpnt"
))
port
map
(
rst_n_i
=>
sys_rst_n_i
,
clk_i
=>
clk_ref_i
,
clk_dmtd_i
=>
clk_dmtd_i
,
clk_aux_i
=>
clk_aux_i
,
input_vector_i
=>
DUT_in_vector
,
output_vector_o
=>
DUT_out_vector
);
end
generate
;
FAKE_IN
:
fake_in_out
generic
map
(
g_in_bits
=>
g_top_in_bits
,
...
...
top/module_test/scb_top_synthesis.vhd
View file @
bd2d43d2
...
...
@@ -293,7 +293,7 @@ begin
generic
map
(
g_top_in_bits
=>
c_top_in_bits
,
g_top_out_bits
=>
c_top_out_bits
,
g_module_name
=>
"
Pstats
"
g_module_name
=>
"
Endpnt
"
)
port
map
(
sys_rst_n_i
=>
sys_rst_n_i
,
...
...
top/module_test/test_top_pkg.vhd
View file @
bd2d43d2
...
...
@@ -108,6 +108,11 @@ package test_top_pkg is
1
+
-- wb_stall_o
1
;
-- wb_int_o
--===================================================--
-- Endpoint parameters --
--===================================================--
constant
c_ep_input_bits
:
integer
:
=
142
;
constant
c_ep_output_bits
:
integer
:
=
321
;
--===================================================--
-- Components --
...
...
@@ -127,23 +132,39 @@ package test_top_pkg is
);
end
component
;
component
endpoint_vectorized_top
generic
(
g_in_bits
:
integer
;
g_out_bits
:
integer
);
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic
;
input_vector_i
:
in
std_logic_vector
(
g_in_bits
-1
downto
0
);
output_vector_o
:
out
std_logic_vector
(
g_out_bits
-1
downto
0
)
);
end
component
;
--===================================================--
-- Test module parameters --
--===================================================--
-- how many modules are supported
constant
c_nmods
:
integer
:
=
2
;
constant
c_nmods
:
integer
:
=
3
;
-- names of the supported modules
constant
test_mods
:
t_strarr
(
0
to
c_nmods
-1
)
:
=
(
"SWcore"
,
"Pstats"
);
constant
test_mods
:
t_strarr
(
0
to
c_nmods
-1
)
:
=
(
"SWcore"
,
"Pstats"
,
"Endpnt"
);
constant
test_inlen
:
t_lentype
(
0
to
c_nmods
-1
)
:
=
(
c_swcore_input_bits
,
-- SWcore
c_pstats_input_bits
-- Pstats
c_pstats_input_bits
,
-- Pstats
c_ep_input_bits
-- Endpoint
);
constant
test_outlen
:
t_lentype
(
0
to
c_nmods
-1
)
:
=
(
c_swcore_output_bits
,
-- SWcore
c_pstats_output_bits
-- Pstats
c_pstats_output_bits
,
-- Pstats
c_ep_output_bits
-- Endpoint
);
--===================================================--
...
...
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