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White Rabbit Switch - Gateware
Commit ce9a70d6 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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HWIU: add posibility to drive chipscope mux as HWDU can do that

parent 78e9ffc2
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Showing with 76 additions and 18 deletions
modules/wrsw_hwiu/hwinfo_pkg.vhd
View file @ ce9a70d6
......@@ -35,7 +35,8 @@ package hwinfo_pkg is
rst_n_i : in std_logic;
clk_i : in std_logic;
dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others=>'0');
dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others=>'0');
dbg_chps_id_o : out std_logic_vector(7 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
......
modules/wrsw_hwiu/hwiu_wbgen2_pkg.vhd
View file @ ce9a70d6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : hwiu_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrsw_hwiu.wb
-- Created : Mon Jun 3 17:21:40 2013
-- Created : Wed Feb 5 16:15:53 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwiu.wb
......@@ -37,12 +37,14 @@ package hwiu_wbgen2_pkg is
cr_adr_o : std_logic_vector(15 downto 0);
cr_rd_en_o : std_logic;
cr_rd_en_load_o : std_logic;
chps_id_o : std_logic_vector(7 downto 0);
end record;
constant c_hwiu_out_registers_init_value: t_hwiu_out_registers := (
cr_adr_o => (others => '0'),
cr_rd_en_o => '0',
cr_rd_en_load_o => '0'
cr_rd_en_load_o => '0',
chps_id_o => (others => '0')
);
function "or" (left, right: t_hwiu_in_registers) return t_hwiu_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
modules/wrsw_hwiu/hwiu_wishbone_slave.vhd
View file @ ce9a70d6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : hwiu_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wrsw_hwiu.wb
-- Created : Mon Jun 3 17:21:40 2013
-- Created : Wed Feb 5 16:15:53 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwiu.wb
......@@ -21,7 +21,7 @@ entity hwiu_wishbone_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -38,11 +38,12 @@ end hwiu_wishbone_slave;
architecture syn of hwiu_wishbone_slave is
signal hwiu_cr_adr_int : std_logic_vector(15 downto 0);
signal hwiu_chps_id_int : std_logic_vector(7 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -67,6 +68,7 @@ begin
rddata_reg <= "00000000000000000000000000000000";
hwiu_cr_adr_int <= "0000000000000000";
regs_o.cr_rd_en_load_o <= '0';
hwiu_chps_id_int <= "00000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -80,8 +82,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
hwiu_cr_adr_int <= wrdata_reg(15 downto 0);
regs_o.cr_rd_en_load_o <= '1';
......@@ -105,12 +107,43 @@ begin
rddata_reg(29) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.reg_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
hwiu_chps_id_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= hwiu_chps_id_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -130,6 +163,8 @@ begin
-- Read register value
regs_o.cr_rd_en_o <= wrdata_reg(31);
-- register value
-- MUX ID
regs_o.chps_id_o <= hwiu_chps_id_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wrsw_hwiu/wrsw_hwiu.vhd
View file @ ce9a70d6
......@@ -35,9 +35,10 @@ entity wrsw_hwiu is
rst_n_i : in std_logic;
clk_i : in std_logic;
dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others => '0');
dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others => '0');
dbg_chps_id_o : out std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(0 downto 0);
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -63,7 +64,8 @@ architecture behav of wrsw_hwiu is
rst_n_i : in std_logic;
clk_i : in std_logic;
dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0);
dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0);
dbg_chps_id_o : out std_logic_vector(7 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
......@@ -86,14 +88,15 @@ begin
rst_n_i => rst_n_i,
clk_i => clk_i,
dbg_regs_i => dbg_regs_i,
dbg_regs_i => dbg_regs_i,
dbg_chps_id_o => dbg_chps_id_o,
wb_i => wb_in,
wb_o => wb_out
);
wb_in.adr(0) <= wb_adr_i(0);
wb_in.adr(31 downto 0) <= (others => '0');
wb_in.adr(1 downto 0) <= wb_adr_i;
wb_in.adr(31 downto 2) <= (others => '0');
wb_in.dat <= wb_dat_i;
wb_in.cyc <= wb_cyc_i;
wb_in.stb <= wb_stb_i;
......
modules/wrsw_hwiu/wrsw_hwiu.wb
View file @ ce9a70d6
......@@ -70,4 +70,18 @@ peripheral {
};
};
reg {
name = "Choose Chipscope input";
description = "Single chipscope module is connected to a MUX, this register is used to contol the MUX";
prefix = "CHPS_ID";
field {
name = "MUX ID";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/wrsw_hwiu/xwrsw_hwiu.vhd
View file @ ce9a70d6
......@@ -41,7 +41,8 @@ entity xwrsw_hwiu is
rst_n_i : in std_logic;
clk_i : in std_logic;
dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others => '0');
dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others => '0');
dbg_chps_id_o : out std_logic_vector(7 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
......@@ -53,7 +54,7 @@ architecture behav of xwrsw_hwiu is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -113,7 +114,7 @@ begin
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_in.adr(0 downto 0),
wb_adr_i => wb_in.adr(1 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
......@@ -183,4 +184,6 @@ begin
end if;
end process;
dbg_chps_id_o <= wb_regs_out.chps_id_o;
end behav;
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