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Commit d346afae authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[generic-azing]: intermediate backup (input_block, pck_pg_free, aribter)

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modules/wrsw_swcore/swc_core.vhd
View file @ d346afae
......@@ -54,12 +54,18 @@ use work.wrsw_shared_types_pkg.all;
entity swc_core is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer ;--:= c_swc_num_ports
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer --:= c_swc_ctrl_width
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer ;--:= c_swc_num_ports
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ; --:= c_swc_ctrl_width
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
-- probably useless with new memory
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size (xswc_input_block)
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
);
port (
clk_i : in std_logic;
......@@ -241,6 +247,19 @@ architecture rtl of swc_core is
gen_blocks : for i in 0 to g_num_ports-1 generate
INPUT_BLOCK : xswc_input_block
generic map(
g_page_addr_width => g_page_addr_width,
g_num_ports => g_num_ports,
g_prio_width => g_prio_width,
g_max_pck_size_width => g_max_pck_size_width,
g_usecount_width => c_usecount_width,
g_data_width => g_data_width,
g_ctrl_width => g_ctrl_width,
g_input_block_cannot_accept_data => g_input_block_cannot_accept_data,
g_packet_mem_multiply => g_packet_mem_multiply,
g_input_block_fifo_size => g_input_block_fifo_size,
g_input_block_fifo_full_in_advance => g_input_block_fifo_full_in_advance
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......@@ -350,6 +369,11 @@ architecture rtl of swc_core is
PCK_PAGES_FREEEING_MODULE: swc_multiport_pck_pg_free_module
generic map(
g_num_ports => g_num_ports,
g_page_addr_width => g_page_addr_width,
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size
)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
......
modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
View file @ d346afae
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-13
-- Last update: 2010-11-13
-- Last update: 2012-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -35,6 +35,7 @@
-- Revisions :
-- Date Version Author Description
-- 2010-11-16 1.0 mlipinsk Created
-- 2012-02-02 2.0 mlipinsk generic-azed
-------------------------------------------------------------------------------
......@@ -48,31 +49,36 @@ use work.swc_swcore_pkg.all;
entity swc_multiport_pck_pg_free_module is
generic(
g_num_ports : integer ; --:= c_swc_num_ports
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer --:= c_swc_freeing_fifo_size
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ib_force_free_done_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ib_force_free_i : in std_logic_vector(g_num_ports-1 downto 0);
ib_force_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ob_free_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ob_free_done_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ob_free_pgaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ob_free_i : in std_logic_vector(g_num_ports-1 downto 0);
ob_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
ob_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0);
--ll_read_data_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_free_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0);
ll_read_addr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
--ll_read_data_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_force_free_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0)
mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0)
);
end swc_multiport_pck_pg_free_module;
......@@ -84,33 +90,37 @@ begin -- syn
lpd_gen : for i in 0 to c_swc_num_ports-1 generate
lpd_gen : for i in 0 to g_num_ports-1 generate
LPD: swc_pck_pg_free_module
generic map(
g_page_addr_width => g_page_addr_width,
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size
)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
ib_force_free_i => ib_force_free_i(i),
ib_force_free_done_o => ib_force_free_done_o(i),
ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ob_free_i => ob_free_i(i),
ob_free_done_o => ob_free_done_o(i),
ob_free_pgaddr_i => ob_free_pgaddr_i((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ob_free_pgaddr_i => ob_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ll_read_addr_o => ll_read_addr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ll_read_addr_o => ll_read_addr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ll_read_data_i => ll_read_data_i,
ll_read_req_o => ll_read_req_o(i),
ll_read_valid_data_i => ll_read_valid_data_i(i),
mmu_free_o => mmu_free_o(i),
mmu_free_done_i => mmu_free_done_i(i),
mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
mmu_force_free_o => mmu_force_free_o(i),
mmu_force_free_done_i => mmu_force_free_done_i(i),
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width)
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width)
);
......
modules/wrsw_swcore/swc_pck_pg_free_module.vhd
View file @ d346afae
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-15
-- Last update: 2011-03-15
-- Last update: 2012-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -37,6 +37,7 @@
-- Revisions :
-- Date Version Author Description
-- 2010-11-16 1.0 mlipinsk Created
-- 2012-02-02 2.0 mlipinsk generic-azed
-------------------------------------------------------------------------------
......@@ -47,35 +48,38 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
--use work.swc_swcore_pkg.all;
use work.genram_pkg.all;
entity swc_pck_pg_free_module is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer --:= c_swc_freeing_fifo_size
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic;
ib_force_free_done_o : out std_logic;
ib_force_free_pgaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ob_free_i : in std_logic;
ob_free_done_o : out std_logic;
ob_free_pgaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ob_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0)
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0)
);
......@@ -100,15 +104,15 @@ architecture syn of swc_pck_pg_free_module is
signal ob_free_done : std_logic;
signal fifo_wr : std_logic;
signal fifo_data_in : std_logic_vector(c_swc_page_addr_width + 2 - 1 downto 0);
signal fifo_data_in : std_logic_vector(g_page_addr_width + 2 - 1 downto 0);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_data_out : std_logic_vector(c_swc_page_addr_width + 2 - 1 downto 0);
signal fifo_data_out : std_logic_vector(g_page_addr_width + 2 - 1 downto 0);
signal fifo_rd : std_logic;
signal fifo_clean : std_logic;
signal current_page : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal next_page : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal current_page : std_logic_vector(g_page_addr_width - 1 downto 0);
signal next_page : std_logic_vector(g_page_addr_width - 1 downto 0);
signal ll_read_req : std_logic;
......@@ -116,7 +120,7 @@ architecture syn of swc_pck_pg_free_module is
signal mmu_force_free : std_logic;
signal mmu_free : std_logic;
signal ones : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal ones : std_logic_vector(g_page_addr_width - 1 downto 0);
signal freeing_mode : std_logic_vector(1 downto 0);
signal fifo_clear_n : std_logic;
......@@ -144,9 +148,9 @@ begin -- syn
fifo_wr <= '1';
fifo_data_in(c_swc_page_addr_width - 1 downto 0) <= ib_force_free_pgaddr_i;
fifo_data_in(c_swc_page_addr_width) <= '1';
fifo_data_in(c_swc_page_addr_width + 1) <= '0';
fifo_data_in(g_page_addr_width - 1 downto 0) <= ib_force_free_pgaddr_i;
fifo_data_in(g_page_addr_width) <= '1';
fifo_data_in(g_page_addr_width + 1) <= '0';
ib_force_free_done <= '1';
ob_free_done <= '0';
......@@ -155,9 +159,9 @@ begin -- syn
fifo_wr <= '1';
fifo_data_in(c_swc_page_addr_width - 1 downto 0) <= ob_free_pgaddr_i;
fifo_data_in(c_swc_page_addr_width) <= '0';
fifo_data_in(c_swc_page_addr_width + 1) <= '1';
fifo_data_in(g_page_addr_width - 1 downto 0) <= ob_free_pgaddr_i;
fifo_data_in(g_page_addr_width) <= '0';
fifo_data_in(g_page_addr_width + 1) <= '1';
ob_free_done <= '1';
ib_force_free_done <= '0';
......@@ -181,8 +185,8 @@ begin -- syn
-- replaced by GenRams component: TW
U_FIFO: generic_sync_fifo
generic map (
g_data_width => c_swc_page_addr_width + 2,
g_size => c_swc_freeing_fifo_size
g_data_width => g_page_addr_width + 2,
g_size => g_pck_pg_free_fifo_size
)
port map (
rst_n_i => fifo_clear_n,
......@@ -237,8 +241,8 @@ fsm_force_free : process(clk_i, rst_n_i)
when S_READ_FIFO =>
freeing_mode <= fifo_data_out(c_swc_page_addr_width + 2 - 1 downto c_swc_page_addr_width);
current_page <= fifo_data_out(c_swc_page_addr_width - 1 downto 0);
freeing_mode <= fifo_data_out(g_page_addr_width + 2 - 1 downto g_page_addr_width);
current_page <= fifo_data_out(g_page_addr_width - 1 downto 0);
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
......
modules/wrsw_swcore/swc_pck_transfer_input.vhd
View file @ d346afae
......@@ -43,8 +43,8 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
--library work;
--use work.swc_swcore_pkg.all;
entity swc_pck_transfer_input is
......
modules/wrsw_swcore/swc_pck_transfer_output.vhd
View file @ d346afae
......@@ -44,8 +44,8 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
--library work;
--use work.swc_swcore_pkg.all;
entity swc_pck_transfer_output is
......
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ d346afae
......@@ -314,6 +314,21 @@ package swc_swcore_pkg is
end component;
component xswc_input_block is
generic (
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_num_ports : integer ;--:= c_swc_num_ports
g_prio_width : integer ;--:= c_swc_prio_width;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_usecount_width : integer ;--:= c_swc_usecount_width
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ;--:= c_swc_ctrl_width
g_input_block_cannot_accept_data : string := "drop_pck"; --"stall_o", "rty_o" -- Don't CHANGE !
-- probably useless with new memory
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -594,6 +609,11 @@ package swc_swcore_pkg is
end component;
component swc_multiport_pck_pg_free_module is
generic(
g_num_ports : integer ; --:= c_swc_num_ports
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer --:= c_swc_freeing_fifo_size
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -624,31 +644,34 @@ component swc_multiport_pck_pg_free_module is
component swc_pck_pg_free_module is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer --:= c_swc_freeing_fifo_size
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic;
ib_force_free_done_o : out std_logic;
ib_force_free_pgaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ob_free_i : in std_logic;
ob_free_done_o : out std_logic;
ob_free_pgaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ob_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0)
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0)
);
......
modules/wrsw_swcore/xswc_core.vhd
View file @ d346afae
......@@ -53,12 +53,7 @@ use work.wrsw_shared_types_pkg.all;
entity xswc_core is
generic
(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer ;--:= c_swc_num_ports
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer --:= c_swc_ctrl_width
g_num_ports : integer := c_swc_num_ports
);
port (
clk_i : in std_logic;
......@@ -94,12 +89,18 @@ architecture rtl of xswc_core is
component swc_core is
generic(
g_page_addr_width : integer := c_swc_page_addr_width;
g_prio_width : integer := c_swc_prio_width;
g_max_pck_size_width : integer := c_swc_max_pck_size_width;
g_num_ports : integer := c_swc_num_ports;
g_data_width : integer := c_swc_data_width;
g_ctrl_width : integer := c_swc_ctrl_width
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer ;--:= c_swc_num_ports
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ; --:= c_swc_ctrl_width
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
-- probably useless with new memory
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size (xswc_input_block)
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
);
port (
clk_i : in std_logic;
......@@ -140,12 +141,17 @@ begin
U_swc_core: swc_core
generic map(
g_page_addr_width => g_page_addr_width,
g_prio_width => g_prio_width,
g_max_pck_size_width => g_max_pck_size_width,
g_num_ports => g_num_ports,
g_data_width => g_data_width,
g_ctrl_width => g_ctrl_width
g_page_addr_width => c_swc_page_addr_width,
g_prio_width => c_swc_prio_width,
g_max_pck_size_width => c_swc_max_pck_size_width,
g_num_ports => c_swc_num_ports,
g_data_width => c_swc_data_width,
g_ctrl_width => c_swc_ctrl_width,
g_pck_pg_free_fifo_size => c_swc_freeing_fifo_size,
g_input_block_cannot_accept_data => "drop_pck", --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
g_packet_mem_multiply => c_swc_packet_mem_multiply,
g_input_block_fifo_size => c_swc_input_fifo_size,
g_input_block_fifo_full_in_advance => c_swc_fifo_full_in_advance
)
port map (
clk_i => clk_i,
......
modules/wrsw_swcore/xswc_input_block.vhd
View file @ d346afae
This diff is collapsed.
testbench/swcore/xswc_core_7_ports_wrapper.vhd
View file @ d346afae
......@@ -237,13 +237,9 @@ end xswc_core_7_ports_wrapper;
architecture rtl of xswc_core_7_ports_wrapper is
component xswc_core is
generic(
g_page_addr_width : integer := c_swc_page_addr_width;
g_prio_width : integer := c_swc_prio_width;
g_max_pck_size_width : integer := c_swc_max_pck_size_width;
g_num_ports : integer := c_swc_num_ports;
g_data_width : integer := c_swc_data_width;
g_ctrl_width : integer := c_swc_ctrl_width
generic
(
g_num_ports : integer := g_swc_num_ports
);
port (
clk_i : in std_logic;
......@@ -253,24 +249,24 @@ component xswc_core is
-- Fabric I/F : input (comes from the Endpoint)
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in_array(g_swc_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_swc_num_ports-1 downto 0);
snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
-------------------------------------------------------------------------------
-- Fabric I/F : output (goes to the Endpoint)
-------------------------------------------------------------------------------
src_i : in t_wrf_source_in_array(g_swc_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_swc_num_ports-1 downto 0);
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_i : in t_rtu_response_array(c_swc_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(c_swc_num_ports - 1 downto 0)
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
);
end component;
......@@ -281,7 +277,7 @@ end component;
signal src_i : t_wrf_source_in_array(g_swc_num_ports-1 downto 0);
signal src_o : t_wrf_source_out_array(g_swc_num_ports-1 downto 0);
signal rtu_rsp_i : t_rtu_response_array(c_swc_num_ports - 1 downto 0);
signal rtu_rsp_i : t_rtu_response_array(g_swc_num_ports - 1 downto 0);
begin
......
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