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White Rabbit Switch - Gateware
Commit d89af41c authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[new mpm]: debugged input and output (first version which does not loose… 

swcore[new mpm]: debugged input and output (first version which does not loose pages during the basic tests !!!)
parent 0ddb54ad
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modules/wrsw_swcore/xswc_input_block.vhd
View file @ d89af41c
......@@ -550,6 +550,7 @@ architecture syn of xswc_input_block is
s_page_alloc <= S_PCKSTART_SET_USECNT;
pckstart_usecnt_req <= '1';
pckstart_usecnt_pgaddr <= current_pckstart_pageaddr;
pckstart_usecnt_write <= current_usecnt;
pckstart_usecnt_prev <= current_usecnt;
......@@ -557,7 +558,7 @@ architecture syn of xswc_input_block is
interpck_page_alloc_req <= '1';
s_page_alloc <= S_INTERPCK_PAGE_REQ;
pckstart_usecnt_write <= pckstart_usecnt_prev;
pckstart_usecnt_write <= std_logic_vector(to_unsigned(1, g_usecount_width));
else
......@@ -579,6 +580,7 @@ architecture syn of xswc_input_block is
s_page_alloc <= S_PCKSTART_SET_USECNT;
pckstart_usecnt_req <= '1';
pckstart_usecnt_pgaddr <= current_pckstart_pageaddr;
pckstart_usecnt_write <= current_usecnt;
pckstart_usecnt_prev <= current_usecnt;
......@@ -644,7 +646,7 @@ architecture syn of xswc_input_block is
--===========================================================================================
if(rtu_rsp_valid_i = '1' and in_pck_sof = '1') then
if(rtu_drop_i = '1') then
if(rtu_drop_i = '1' or rtu_dst_port_mask_i = zeros) then
s_transfer_pck <= S_DROP_PCK;
elsif(rtu_dst_port_usecnt = pckstart_usecnt_prev) then
s_transfer_pck <= S_TRANSFER;
......@@ -674,7 +676,7 @@ architecture syn of xswc_input_block is
when S_WAIT_RTU_VALID =>
--===========================================================================================
if(rtu_rsp_valid_i = '1') then
if(rtu_drop_i = '1') then
if(rtu_drop_i = '1' or rtu_dst_port_mask_i = zeros) then
s_transfer_pck <= S_DROP_PCK;
elsif(rtu_dst_port_usecnt = pckstart_usecnt_prev) then
s_transfer_pck <= S_TRANSFER;
......@@ -696,7 +698,7 @@ architecture syn of xswc_input_block is
when S_WAIT_SOF =>
--===========================================================================================
if(in_pck_sof = '1') then
if(current_drop = '1') then
if(current_drop = '1' or pta_mask = zeros) then
s_transfer_pck <= S_DROP_PCK;
elsif(current_usecnt = pckstart_usecnt_prev) then
s_transfer_pck <= S_TRANSFER;
......@@ -909,7 +911,7 @@ architecture syn of xswc_input_block is
snk_stall_force_l <= '1';
-- pck has not been transferred to the outputs yet, so we need to free on the inputs
if(s_transfer_pck /= S_PCK_TRANSFERED and s_transfer_pck /= S_PCK_TRANSFER) then
if(s_transfer_pck /= S_PCK_TRANSFERED and s_transfer_pck /= S_TRANSFER) then
mmu_force_free_addr <= current_pckstart_pageaddr;
......@@ -1015,6 +1017,7 @@ architecture syn of xswc_input_block is
if(ready_for_next_pck = '1' ) then -- un-stuck the input :)
snk_stall_force_h <= '0';
drop_on_stuck <= '1';
in_pck_dat_d0 <= (others=>'0');
in_pck_sel_d0 <= (others=>'0');
in_pck_sel_d1 <= (others=>'0');
......@@ -1081,6 +1084,10 @@ architecture syn of xswc_input_block is
if(in_pck_sof = '1' and in_pck_drop_on_sof = '0' and drop_on_stuck = '0' ) then
pckstart_page_in_advance <= '0';
elsif(in_pck_sof = '1' and in_pck_drop_on_sof = '0' and drop_on_stuck = '1' and ready_for_next_pck = '1' ) then
-- this is a special case when we go to RCV_DATA from INPUT_STUCK (p_rcv_pck_fsm)
-- in such case we also use new page
pckstart_page_in_advance <= '0';
elsif(mmu_page_alloc_done_i = '1' and pckstart_page_alloc_req = '1') then
pckstart_page_in_advance <= '1';
end if;
......
modules/wrsw_swcore/xswc_output_block.vhd
View file @ d89af41c
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testbench/swcore/swc_core_generic.sv
View file @ d89af41c
......@@ -277,7 +277,7 @@ module main_generic;
sum_tx = 0;
sum_rx = 0;
for(i=0;i<11;i++)
for(i=0;i<`c_num_ports;i++)
begin
for(j=0;j<`c_num_ports;j++) sum_tx_by_port[i] += tx_cnt_by_port[j][i];
for(j=0;j<`c_num_ports;j++) sum_rx_by_port[i] += rx_cnt_by_port[i][j];
......@@ -302,8 +302,14 @@ module main_generic;
for(i=0;i<`c_num_ports;i++)
begin
s = $psprintf("",i);
for(int j=0;j<`c_num_ports;j++) s = {s, $psprintf(" %2d>%2d |",tx_cnt_by_port[i][j],rx_cnt_by_port[i][j])};
$display("TX Port %2d : %s",i,s);
for(int j=0;j<`c_num_ports;j++)
begin
if(tx_cnt_by_port[i][j] == rx_cnt_by_port[i][j])
s = {s, $psprintf(" %2d>%2d |",tx_cnt_by_port[i][j],rx_cnt_by_port[i][j])};
else
s = {s, $psprintf("*%2d>%2d*|",tx_cnt_by_port[i][j],rx_cnt_by_port[i][j])};
end
$display("TX Port %2d : %s",i,s);
end
$display("%s",d1);
......@@ -365,6 +371,8 @@ module main_generic;
sink[17] = new(U_wrf_sink[17].get_accessor());
*/
endfunction
/*
......@@ -385,7 +393,7 @@ module main_generic;
EthPacket pkt, tmpl;
EthPacket txed[$];
EthPacketGenerator gen;
int i,j;
int j;
int n_ports = `c_num_ports;
bit [`c_num_ports:0] mask;
// initialization
......@@ -403,22 +411,30 @@ module main_generic;
//for(j=0;j<`c_num_ports;j++) begin
// U_wrf_sink[0].permanent_stall_enable();
for(j=0;j<16;j++) begin
fork
automatic int p = j;
for(i=0; i<16; i++) begin
mask = mask^(1<<(i%(`c_num_ports)));
//mask =1<<p;
//send_random_packet(src,txed, 0 , 0,7 , mask);
//send_random_packet(src,txed, j, 0,7 , 16'hFFFF);
//$display("in fork %d",p);
send_random_packet(src,txed, p, 0,7 , mask);
end
join
//wait_cycles(500);
// fork
// begin
automatic int p = j;
//automatic bit [`c_num_ports:0] mask;
for(int z=0; z<16; z++) begin
mask = mask^(1<<(z%(`c_num_ports)));
//mask =1<<p;
//send_random_packet(src,txed, 0 , 0,7 , mask);
//send_random_packet(src,txed, j, 0,7 , 16'hFFFF);
//$display("in fork %d",p);
send_random_packet(src,txed, p, 0,7 , mask);
//wait_cycles(100);
end
// end
// join
end
wait_cycles(10000);
//U_wrf_sink[0].permanent_stall_disable();
wait_cycles(80000);
wait_cycles(60000);
transferReport(); // here we wait for all pcks to be received and then make statistics
memoryLeakageReport();
......@@ -549,7 +565,7 @@ module main_generic;
begin
s = "";
for(j=0;j<`c_num_ports;j++) s = {s, $psprintf("%2d:%2d|",alloc_table[i].usecnt[j],alloc_table[i].port[j])};
$display("Page %4d: alloc = %4d [%s]",i,alloc_table[i].cnt,s);
$display("Page %4d[0x0%x: alloc = %4d [%s]",i,i,alloc_table[i].cnt,s);
cnt++;
end
......
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