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White Rabbit Switch - Gateware
Commit db3fb858 authored by li hongming's avatar li hongming
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add clk_ext_10m_i pin.

parent c9e54723
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Showing with 12 additions and 14 deletions
top/scb_18ports/scb_top_synthesis.ucf
View file @ db3fb858
......@@ -10,7 +10,7 @@ NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
#NET "clk_ext_i" LOC=K13;
NET "clk_ext_i" LOC=K13;
NET "clk_aux_p_o" LOC=B20;
NET "clk_aux_n_o" LOC=C19;
#NET "clk_500_o" LOC=AM33;
......@@ -107,7 +107,6 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
# NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ext_pll_cs_n_o" LOC = AD27;
......@@ -303,7 +302,9 @@ NET "clk_gtx4_7" TNM_NET = gtx4_7_clk;
NET "clk_gtx8_11" TNM_NET = gtx8_11_clk;
NET "clk_gtx12_15" TNM_NET = gtx12_15_clk;
NET "clk_gtx16_19" TNM_NET = gtx16_19_clk;
NET "clk_ext_i" TNM_NET = fpga_clk_10mhz;
TIMESPEC TS_fpga_clk_10mhz = PERIOD "fpga_clk_10mhz" 100 ns HIGH 50%;
TIMESPEC TS_fpga_clk_25mhz = PERIOD "fpga_clk_25mhz" 40ns HIGH 50%;
TIMESPEC TS_fpga_clk_dmtd = PERIOD "fpga_clk_dmtd" 16ns HIGH 50%;
TIMESPEC TS_fpga_clk_ref = PERIOD "fpga_clk_ref" 16ns HIGH 50%;
......@@ -1461,4 +1462,4 @@ AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
\ No newline at end of file
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
top/scb_18ports/scb_top_synthesis.vhd
View file @ db3fb858
......@@ -72,7 +72,7 @@ entity scb_top_synthesis is
fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
--clk_ext_i : in std_logic;
clk_ext_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
......@@ -554,10 +554,10 @@ begin
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
--U_CLKEXT_BUF: IBUFG
-- port map (
-- I => clk_ext_i,
-- O => clk_ext);
U_CLKEXT_BUF: IBUFG
port map (
I => clk_ext_i,
O => clk_ext);
gen_with_ext_AD9516 : if (g_with_ext_AD9516) generate
......@@ -783,7 +783,6 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
--pll_status_i => clk_ext,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ db3fb858
......@@ -115,7 +115,6 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
# NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ext_pll_cs_n_o" LOC = AD27;
......@@ -300,7 +299,9 @@ NET "clk_ref" TNM_NET = fpga_clk_ref;
#NET "clk_gtx8_11" TNM_NET = gtx8_11_clk;
#NET "clk_gtx12_15" TNM_NET = gtx12_15_clk;
NET "clk_gtx16_19" TNM_NET = gtx16_19_clk;
NET "clk_ext_i" TNM_NET = fpga_clk_10mhz;
TIMESPEC TS_fpga_clk_10mhz = PERIOD "fpga_clk_10mhz" 100 ns HIGH 50%;
TIMESPEC TS_fpga_clk_25mhz = PERIOD "fpga_clk_25mhz" 40ns HIGH 50%;
TIMESPEC TS_fpga_clk_dmtd = PERIOD "fpga_clk_dmtd" 16ns HIGH 50%;
TIMESPEC TS_fpga_clk_ref = PERIOD "fpga_clk_ref" 16ns HIGH 50%;
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ db3fb858
......@@ -72,7 +72,7 @@ entity scb_top_synthesis is
fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
--clk_ext_i : in std_logic;
clk_ext_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
......@@ -124,7 +124,6 @@ entity scb_top_synthesis is
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -361,7 +360,6 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -793,7 +791,6 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
-- pll_status_i => clk_ext,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......
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