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White Rabbit Switch - Gateware
Commit dd7d62d9 authored by Adam Wujek's avatar Adam Wujek
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revert add generated files by python 

Signed-off-by: 's avatarAdam Wujek <dev_public@wujek.eu>
parent 0744e981
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      .gitlab-ci.yml
      View file @ dd7d62d9
      ......@@ -48,11 +48,12 @@ job_scb_top_8p_syn:
      - du -sh *
      - cd top/bare_top
      - which python
      #- python2.7 gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_18p --ver "14.7"
      - python gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_18p --ver "14.7"
      - cat synthesis_descriptor.vhd
      - find / | grep hdlmake
      # TODO: remove, called from syn_pre_project_cmd
      - cd ../../modules/wrsw_hwiu
      #- python2.7 gen_ver.py
      - python gen_ver.py
      - cat gw_ver_pkg.vhd
      - cd ../../syn/scb_8ports
      - which hdlmake
      ......@@ -89,11 +90,12 @@ job_scb_top_18p_syn:
      - source ~/setup_ise147.sh
      - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
      - cd top/bare_top
      #- python2.7 gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_8p --ver "14.7"
      - python gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_8p --ver "14.7"
      - cat synthesis_descriptor.vhd
      - find / | grep hdlmake
      # TODO: remove, called from syn_pre_project_cmd
      - cd ../../modules/wrsw_hwiu
      #- python gen_ver.py
      - python gen_ver.py
      - cat gw_ver_pkg.vhd
      - cd ../../syn/scb_18ports
      - which hdlmake
      ......
      modules/wrsw_hwiu/gw_ver_pkg.vhd deleted 100644 → 0
      View file @ 0744e981
      library ieee;
      use ieee.std_logic_1164.all;
      --generated automatically by gen_ver.py script--
      package hwver_pkg is
      constant c_build_date : std_logic_vector(31 downto 0) := x"04051800";
      constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"0ed1937e";
      constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0434f154";
      constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"075bb7bb";
      end package;
      syn/scb_8ports/Manifest.py
      View file @ dd7d62d9
      ......@@ -10,7 +10,7 @@ syn_grade = "-1"
      syn_package = "ff1156"
      syn_top = "scb_top_synthesis"
      syn_project = "test_scb.xise"
      syn_pre_project_cmd=""
      syn_pre_project_cmd="python ../../modules/wrsw_hwiu/gen_ver.py"
      syn_post_bitstream_cmd="bitgen -intstyle ise -f scb_top_synthesis.ut -g Binary:yes scb_top_synthesis.ncd"
      modules = { "local" : [ "../../top/scb_8ports",
      ......
      top/bare_top/synthesis_descriptor.vhd deleted 100644 → 0
      View file @ 0744e981
      -- package generated automatically by gen_sdbsyn.py script --
      library ieee;
      use ieee.std_logic_1164.all;
      use work.wishbone_pkg.all;
      package synthesis_descriptor is
      constant c_sdb_repo_url : t_sdb_repo_url := (
      repo_url => "ssh://git@ohwr.org:7999/project/wr-switch-hdl.git ");
      constant c_sdb_top_syn_info : t_sdb_synthesis := (
      syn_module_name => "WRS_18p+ ",
      syn_commit_id => "28a57ea7 ",
      syn_tool_name => "ISE ",
      syn_tool_version => x"00000147",
      syn_date => x"20240506",
      syn_username => "CI Maciej Lipin");
      constant c_sdb_general_cores_syn_info : t_sdb_synthesis := (
      syn_module_name => "general-cores ",
      syn_commit_id => "434f1546 ",
      syn_tool_name => " ",
      syn_tool_version => x"00000000",
      syn_date => x"00000000",
      syn_username => " ");
      constant c_sdb_wr_cores_syn_info : t_sdb_synthesis := (
      syn_module_name => "wr-cores ",
      syn_commit_id => "75bb7bbf ",
      syn_tool_name => " ",
      syn_tool_version => x"00000000",
      syn_date => x"00000000",
      syn_username => " ");
      end package;
      \ No newline at end of file
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