Skip to content

W
White Rabbit Switch - Gateware
Commit dddedff7 authored by Maciej Lipinski's avatar Maciej Lipinski
Browse files
Options

Importing swcore to the new repo: adding swcore files from the old repo… 

Importing swcore to the new repo: adding swcore files from the old repo (hopefully with the history) to the new repo
parents 5c598e8e 5aaaade6
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 8838 additions and 0 deletions
modules/wrsw_swcore/Makefile 0 → 100644
View file @ dddedff7
SRCS_VHDL = swc_swcore_pkg.vhd \
swc_block_alloc.vhd \
swc_core.vhd \
swc_input_block.vhd \
swc_lost_pck_dealloc.vhd \
swc_multiport_linked_list.vhd \
swc_multiport_page_allocator.vhd \
swc_multiport_pck_pg_free_module.vhd \
swc_ob_prio_queue.vhd \
swc_output_block.vhd \
swc_packet_mem.vhd \
swc_packet_mem_read_pump.vhd \
swc_packet_mem_write_pump.vhd \
swc_page_alloc.vhd \
swc_pck_pg_free_module.vhd \
swc_pck_transfer_arbiter.vhd \
swc_pck_transfer_input.vhd \
swc_pck_transfer_output.vhd \
swc_prio_encoder.vhd \
swc_rr_arbiter.vhd
WORK = work
#directories in which we should search for the VHDL/verilog source files
VPATH =
include ../../scripts/modules.mk
modules/wrsw_swcore/TODOlist 0 → 100644
View file @ dddedff7
- synchronize local *platform_specific.vhd* and *generic_ssram_dualport_singleclock.vhd* with main (in hdl/latform/altera)
- fix swc_packet_mem_read_pump.vhd
\ No newline at end of file
modules/wrsw_swcore/generic_ssram_dualport_singleclock.vhd 0 → 100644
View file @ dddedff7
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: aaa.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity generic_ssram_dualport_singleclock is
generic (
g_width : natural := 8;
g_addr_bits : natural := 10;
g_size : natural := 1024;
g_init_file : string := "UNUSED");
port
(
data_i : in std_logic_vector (g_width-1 downto 0);
clk_i : in std_logic;
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0)
);
end generic_ssram_dualport_singleclock;
architecture SYN of generic_ssram_dualport_singleclock is
signal sub_wire0 : std_logic_vector (g_width-1 downto 0);
component altsyncram
generic (
address_aclr_b : string;
address_reg_b : string;
clock_enable_input_a : string;
clock_enable_input_b : string;
clock_enable_output_b : string;
intended_device_family : string;
lpm_type : string;
numwords_a : natural;
numwords_b : natural;
operation_mode : string;
outdata_aclr_b : string;
outdata_reg_b : string;
power_up_uninitialized : string;
read_during_write_mode_mixed_ports : string;
widthad_a : natural;
widthad_b : natural;
width_a : natural;
width_b : natural;
INIT_FILE : string ;
width_byteena_a : natural
);
port (
wren_a : in std_logic;
clock0 : in std_logic;
address_a : in std_logic_vector (g_addr_bits-1 downto 0);
address_b : in std_logic_vector (g_addr_bits-1 downto 0);
q_b : out std_logic_vector (g_width-1 downto 0);
data_a : in std_logic_vector (g_width-1 downto 0)
);
end component;
begin
q_o <= sub_wire0(g_width-1 downto 0);
altsyncram_component : altsyncram
generic map (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => g_size,
numwords_b => g_size,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => g_addr_bits,
widthad_b => g_addr_bits,
width_a => g_width,
width_b => g_width,
width_byteena_a => 1,
INIT_FILE => g_init_file
)
port map (
wren_a => wr_en_i,
clock0 => clk_i,
address_a => wr_addr_i,
address_b => rd_addr_i,
data_a => data_i,
q_b => sub_wire0
);
end SYN;
modules/wrsw_swcore/l0_init.mif 0 → 100644
View file @ dddedff7
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II generated Memory Initialization File (.mif)
WIDTH=32;
DEPTH=32;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
[0..31] : 4294967295;
END;
modules/wrsw_swcore/manifest.py 0 → 100644
View file @ dddedff7
files = ["swc_swcore_pkg.vhd",
"swc_block_alloc.vhd",
"swc_core.vhd",
"swc_input_block.vhd",
"swc_lost_pck_dealloc.vhd",
"swc_multiport_linked_list.vhd",
"swc_multiport_page_allocator.vhd",
"swc_multiport_pck_pg_free_module.vhd",
"swc_ob_prio_queue.vhd",
"swc_output_block.vhd",
"swc_packet_mem.vhd",
"swc_packet_mem_read_pump.vhd",
"swc_packet_mem_write_pump.vhd",
"swc_page_alloc.vhd",
"swc_pck_pg_free_module.vhd",
"swc_pck_transfer_arbiter.vhd",
"swc_pck_transfer_input.vhd",
"swc_pck_transfer_output.vhd",
"swc_prio_encoder.vhd",
"swc_rr_arbiter.vhd",
"generic_ssram_dualport_singleclock.vhd"]
modules/wrsw_swcore/platform_specific.vhd 0 → 100644
View file @ dddedff7
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lpm;
use lpm.all;
-------------------------------------------------------------------------------
package platform_specific is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component generic_async_fifo_2stage
generic (
g_width : natural;
g_depth : natural;
g_almostfull_bit_threshold : natural);
port (
clear_i : in std_logic := '0';
d_i : in std_logic_vector (g_width-1 downto 0);
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
almost_full_o : out std_logic);
end component;
component generic_ssram_dualport
generic (
g_width : natural;
g_addr_bits : natural;
g_size : natural);
port (
data_i : in std_logic_vector (g_width-1 downto 0);
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
rd_clk_i : in std_logic;
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_clk_i : in std_logic;
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0));
end component;
component generic_ssram_dualport_singleclock
generic (
g_width : natural;
g_addr_bits : natural;
g_size : natural;
g_init_file : string := "UNUSED");
port (
data_i : in std_logic_vector (g_width-1 downto 0);
clk_i : in std_logic;
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0));
end component;
component alt_clock_divider
port (
inclk0 : in std_logic := '0';
c0 : out std_logic;
c1 : out std_logic;
locked : out std_logic);
end component;
component generic_sync_fifo
generic (
g_width : natural;
g_depth : natural;
g_depth_log2 : natural);
port (
clk_i : in std_logic;
clear_i : in std_logic := '0';
wr_req_i : in std_logic;
d_i : in std_logic_vector (g_width-1 downto 0);
rd_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
empty_o : out std_logic;
full_o : out std_logic;
usedw_o : out std_logic_vector(g_depth_log2-1 downto 0));
end component;
component generic_pipelined_multiplier
generic (
g_width_a : natural;
g_width_b : natural;
g_width_out : natural;
g_sign_mode : string);
port (
clk_i : in std_logic;
a_i : in std_logic_vector(g_width_a -1 downto 0);
b_i : in std_logic_vector(g_width_b -1 downto 0);
q_o : out std_logic_vector(g_width_out-1 downto 0));
end component;
end platform_specific;
-------------------------------------------------------------------------------
modules/wrsw_swcore/swc_block_alloc.vhd 0 → 100644
View file @ dddedff7
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity swc_block_allocator is
generic (
g_num_blocks : integer := 2048;
g_log2_num_blocks : integer := 13;
g_usecount_bits : integer := 4
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
idle_o : out std_logic;
alloc_rq_i : in std_logic;
alloc_size_i : in std_logic_vector (7 downto 0);
alloc_done_o : out std_logic;
alloc_nomem_o : out std_logic;
alloc_use_count_i : in std_logic_vector(g_usecount_bits-1 downto 0);
alloc_addr_o : out std_logic_vector (g_log2_num_blocks-1 downto 0);
free_rq_i : in std_logic;
free_addr_i : in std_logic_vector(g_log2_num_blocks-1 downto 0);
free_done_o : out std_logic
);
end swc_block_allocator;
architecture syn of swc_block_allocator is
constant c_l1_size : integer := g_num_blocks/32;
signal l1_full : std_logic_vector(c_l1_size-1 downto 0); -- 1 means block is
-- full
signal l1_empty : std_logic_vector(c_l1_size-1 downto 0); -- 1 means block is
-- empty
type t_state is (IDLE, ALLOC_LOOKUP_L1);
begin -- syn
process (clk_i, rst_n_i)
begin -- process
if rising_edge(clk_i) then
if(rst_n_i = '0') then
l1_full <= (others => '0');
l1_empty <= (others => '1');
else
end if;
end if;
end process;
end syn;
modules/wrsw_swcore/swc_core.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_core_signle_port.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_input_block.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_lost_pck_dealloc.vhd 0 → 100644
View file @ dddedff7
-------------------------------------------------------------------------------
-- Title : Lost Pck Deallocator
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_lost_pck_dealloc.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-15
-- Last update: 2011-03-15
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
--
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-15 1.0 mlipinsk Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.genram_pkg.all;
entity swc_lost_pck_dealloc is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic;
ib_force_free_done_o : out std_logic;
ib_force_free_pgaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ob_force_free_i : in std_logic;
ob_force_free_done_o : out std_logic;
ob_force_free_pgaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0)
);
end swc_lost_pck_dealloc;
architecture syn of swc_lost_pck_dealloc is
type t_state is (S_IDLE,
S_REQ_READ_FIFO,
S_READ_FIFO,
S_READ_NEXT_PAGE_ADDR,
S_FREE_CURRENT_PAGE_ADDR
);
signal state : t_state;
signal ib_force_free_done : std_logic;
signal ob_force_free_done : std_logic;
signal fifo_wr : std_logic;
signal fifo_data_in : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_data_out : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal fifo_rd : std_logic;
signal fifo_clean : std_logic;
signal current_page : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal next_page : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal ll_read_req : std_logic;
signal mmu_force_free : std_logic;
signal ones : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
begin -- syn
ones <= (others => '1');
INPUT: process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
ib_force_free_done <= '0';
ob_force_free_done <= '0';
fifo_wr <= '0';
fifo_data_in <= (others => '0');
else
-- serve Input request, unless it's already served ( ib_force_free_done = '1')
if(ib_force_free_i = '1' and fifo_full = '0' and ib_force_free_done = '0') then
fifo_wr <= '1';
fifo_data_in <= ib_force_free_pgaddr_i;
ib_force_free_done <= '1';
ob_force_free_done <= '0';
elsif(ob_force_free_done = '1' and fifo_full = '0') then
fifo_wr <= '1';
fifo_data_in <= ob_force_free_pgaddr_i;
ob_force_free_done <= '1';
ib_force_free_done <= '0';
else
fifo_wr <= '0';
fifo_data_in <= (others => '0');
ib_force_free_done <= '0';
ob_force_free_done <= '0';
end if;
end if;
end if;
end process;
U_FIFO: generic_sync_fifo
generic map(
g_data_width => c_swc_page_addr_width,
g_size => 16
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
we_i => fifo_wr,
d_i => fifo_data_in,
rd_i => fifo_rd,
q_o => fifo_data_out,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => open
);
fsm_force_free : process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
--================================================
state <= S_IDLE;
fifo_rd <= '0';
current_page <= (others => '0');
next_page <= (others => '0');
ll_read_req <= '0';
mmu_force_free <= '0';
--================================================
else
-- main finite state machine
case state is
when S_IDLE =>
fifo_rd <= '0';
mmu_force_free <= '0';
if(fifo_empty = '0') then
fifo_rd <= '1';
state <= S_REQ_READ_FIFO;
end if;
when S_REQ_READ_FIFO =>
fifo_rd <= '0';
state <= S_READ_FIFO;
when S_READ_FIFO =>
current_page <= fifo_data_out;
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
when S_READ_NEXT_PAGE_ADDR =>
if(ll_read_valid_data_i = '1') then
ll_read_req <= '0';
state <= S_FREE_CURRENT_PAGE_ADDR;
next_page <= ll_read_data_i;
mmu_force_free <= '1';
end if;
when S_FREE_CURRENT_PAGE_ADDR =>
if(mmu_force_free_done_i = '1') then
mmu_force_free <= '0';
if(next_page = ones ) then
state <= S_IDLE;
else
current_page <= next_page;
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
end if;
end if;
when others =>
state <= S_IDLE;
fifo_rd <= '0';
current_page <= (others => '0');
next_page <= (others => '0');
ll_read_req <= '0';
mmu_force_free <= '0';
end case;
end if;
end if;
end process;
ll_read_addr_o <= current_page;
ll_read_req_o <= ll_read_req;
mmu_force_free_pgaddr_o <= current_page;
mmu_force_free_o <= mmu_force_free;
ib_force_free_done_o <= ib_force_free_done;
ob_force_free_done_o <= ob_force_free_done;
end syn;
modules/wrsw_swcore/swc_multiport_linked_list.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_multiport_lost_pck_dealloc.vhd 0 → 100644
View file @ dddedff7
-------------------------------------------------------------------------------
-- Title : multiport lost pck deallocator
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_multiport_plost_pck_dealloc.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-13
-- Last update: 2010-11-13
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-13 1.0 mlipinsk Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.platform_specific.all;
entity swc_multiport_lost_pck_dealloc is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ib_force_free_done_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ob_force_free_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ob_force_free_done_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ob_force_free_pgaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0);
--ll_read_data_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0)
);
end swc_multiport_lost_pck_dealloc;
architecture syn of swc_multiport_lost_pck_dealloc is
begin -- syn
lpd_gen : for i in 0 to c_swc_num_ports-1 generate
LPD: swc_lost_pck_dealloc
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
ib_force_free_i => ib_force_free_i(i),
ib_force_free_done_o => ib_force_free_done_o(i),
ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ob_force_free_i => ob_force_free_i(i),
ob_force_free_done_o => ob_force_free_done_o(i),
ob_force_free_pgaddr_i => ob_force_free_pgaddr_i((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ll_read_addr_o => ll_read_addr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
--ll_read_data_i => ll_read_data_i((i+1)*c_swc_num_ports - 1 downto i * c_swc_num_ports),
ll_read_data_i => ll_read_data_i,
ll_read_req_o => ll_read_req_o(i),
ll_read_valid_data_i => ll_read_valid_data_i(i),
mmu_force_free_o => mmu_force_free_o(i),
mmu_force_free_done_i => mmu_force_free_done_i(i),
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width)
);
end generate lpd_gen;
end syn;
modules/wrsw_swcore/swc_multiport_page_allocator.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd 0 → 100644
View file @ dddedff7
-------------------------------------------------------------------------------
-- Title : Pck's Pages Freeing Module
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_multiport_pck_pg_free_module.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-13
-- Last update: 2010-11-13
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: this modules free pages of read/dropped modules
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-16 1.0 mlipinsk Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.platform_specific.all;
entity swc_multiport_pck_pg_free_module is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ib_force_free_done_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ob_free_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ob_free_done_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ob_free_pgaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0);
--ll_read_data_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_free_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0);
mmu_force_free_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0)
);
end swc_multiport_pck_pg_free_module;
architecture syn of swc_multiport_pck_pg_free_module is
begin -- syn
lpd_gen : for i in 0 to c_swc_num_ports-1 generate
LPD: swc_pck_pg_free_module
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
ib_force_free_i => ib_force_free_i(i),
ib_force_free_done_o => ib_force_free_done_o(i),
ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ob_free_i => ob_free_i(i),
ob_free_done_o => ob_free_done_o(i),
ob_free_pgaddr_i => ob_free_pgaddr_i((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ll_read_addr_o => ll_read_addr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ll_read_data_i => ll_read_data_i,
ll_read_req_o => ll_read_req_o(i),
ll_read_valid_data_i => ll_read_valid_data_i(i),
mmu_free_o => mmu_free_o(i),
mmu_free_done_i => mmu_free_done_i(i),
mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
mmu_force_free_o => mmu_force_free_o(i),
mmu_force_free_done_i => mmu_force_free_done_i(i),
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width)
);
end generate lpd_gen;
end syn;
modules/wrsw_swcore/swc_ob_prio_queue.vhd 0 → 100644
View file @ dddedff7
-------------------------------------------------------------------------------
-- Title : Priority Queue
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_ob_prio_queue.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
-- Last update: 2010-11-03
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-09 1.0 mlipinsk created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
entity swc_ob_prio_queue is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- I/F
-------------------------------------------------------------------------------
write_i : in std_logic;
read_i : in std_logic;
not_full_o : out std_logic;
not_empty_o : out std_logic;
-------------------------------------------------------------------------------
-- I/F with SRAM
-------------------------------------------------------------------------------
wr_en_o : out std_logic;
wr_addr_o : out std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0);
rd_addr_o : out std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0)
);
end swc_ob_prio_queue;
architecture behavoural of swc_ob_prio_queue is
signal head : std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0);
signal tail : std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0);
signal not_full : std_logic;
signal not_empty : std_logic;
begin -- behavoural
sram_if : process (clk_i, rst_n_i)
begin -- process
if rising_edge(clk_i) then
if(rst_n_i = '0') then
head <= (others => '0');
tail <= (others => '0');
else
if(write_i = '1' and not_full = '1') then
head <= std_logic_vector(unsigned(head) + 1);
end if;
if(read_i = '1' and not_empty = '1') then
tail <= std_logic_vector(unsigned(tail) + 1);
end if;
end if;
end if;
end process;
not_full <= '0' when (head = std_logic_vector(unsigned(tail) - 1)) else '1';
not_empty <= '0' when (tail = head ) else '1';
wr_addr_o <= head;
rd_addr_o <= tail;
wr_en_o <= write_i and not_full;
not_full_o <= not_full;
not_empty_o <= not_empty;
end behavoural;
\ No newline at end of file
modules/wrsw_swcore/swc_output_block.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_packet_mem.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_packet_mem_read_pump.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_packet_mem_write_pump.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_page_alloc.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_pck_pg_free_module.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_pck_transfer_input.vhd 0 → 100644
View file @ dddedff7
-------------------------------------------------------------------------------
-- Title : Packet Transfer Input
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_pck_transfer_input.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
-- Last update: 2010-11-03
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-03 1.0 mlipinsk created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
entity swc_pck_transfer_input is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- I/F with pck transfer output (PTO)
-------------------------------------------------------------------------------
pto_transfer_pck_o : out std_logic;
pto_pageaddr_o : out std_logic_vector(c_swc_page_addr_width - 1 downto 0);
pto_output_mask_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
pto_read_mask_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
pto_prio_o : out std_logic_vector(c_swc_prio_width - 1 downto 0);
pto_pck_size_o : out std_logic_vector(c_swc_max_pck_size_width - 1 downto 0);
-------------------------------------------------------------------------------
-- I/F with Input Block (IB)
-------------------------------------------------------------------------------
-- indicates the beginning of the package, strobe
ib_transfer_pck_i : in std_logic;
-- array of pages' addresses to which ports want to write
ib_pageaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
-- destination mask - indicates to which ports the packet should be
-- forwarded
ib_mask_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
ib_prio_i : in std_logic_vector(c_swc_prio_width - 1 downto 0);
ib_pck_size_i : in std_logic_vector(c_swc_max_pck_size_width - 1 downto 0);
ib_transfer_ack_o : out std_logic;
ib_busy_o : out std_logic
);
end swc_pck_transfer_input;
architecture syn of swc_pck_transfer_input is
signal ib_transfer_ack: std_logic;
signal ib_pageaddr : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal ib_prio : std_logic_vector(c_swc_prio_width - 1 downto 0);
signal ib_pck_size : std_logic_vector(c_swc_max_pck_size_width - 1 downto 0);
signal ib_mask : std_logic_vector(c_swc_num_ports - 1 downto 0);
--signal pto_read_mask : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal pto_output_mask : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal zeros : std_logic_vector(c_swc_num_ports - 1 downto 0);
begin --arch
zeros <= (others => '0');
input: process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
--===================================================
ib_mask <= (others => '0');
--pto_read_mask <= (others => '0');
pto_output_mask <= (others => '0');
ib_prio <= (others => '0');
ib_pck_size <= (others => '0');
ib_pageaddr <= (others => '0');
ib_transfer_ack <= '0';
--===================================================
else
if(ib_transfer_pck_i = '1' and pto_output_mask = zeros) then
ib_mask <= ib_mask_i;
ib_prio <= ib_prio_i;
ib_pageaddr <= ib_pageaddr_i;
ib_pck_size <= ib_pck_size_i;
end if;
if(ib_transfer_pck_i = '1' and pto_output_mask = zeros) then
--pto_read_mask <= (others => '0');
pto_output_mask <= ib_mask_i;--(others => '0');
else
-- pto_read_mask <= pto_read_mask or (pto_read_mask_i and ib_mask);
-- pto_output_mask <= (((pto_read_mask_i and ib_mask) -- filter read mask, if a port which
-- -- is not supposed to read the data, reads it
-- -- we see no difference
-- or pto_read_mask) -- add to the mask of the outputs_block which
-- -- already read the data, the one currently reading
-- xor ib_mask);
--
pto_output_mask <= (not(pto_read_mask_i and ib_mask) ) and pto_output_mask;
end if;
if(ib_transfer_ack = '1') then
ib_transfer_ack <= '0';
elsif(ib_transfer_pck_i = '1' and pto_output_mask = zeros) then
ib_transfer_ack <= '1';
else
ib_transfer_ack <= '0';
end if;
--
--===================================================
end if;
end if;
end process;
pto_output_mask_o <= pto_output_mask;
pto_transfer_pck_o <= '0';
pto_pageaddr_o <= ib_pageaddr;
pto_prio_o <= ib_prio;
pto_pck_size_o <= ib_pck_size;
ib_transfer_ack_o <= ib_transfer_ack;
ib_busy_o <= '0' when (pto_output_mask = zeros) else '1';
end syn; -- arch
\ No newline at end of file
modules/wrsw_swcore/swc_pck_transfer_output.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_prio_encoder.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
modules/wrsw_swcore/swc_rr_arbiter.vhd 0 → 100644
View file @ dddedff7
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment