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White Rabbit Switch - Gateware
Commit e44d45dc authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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match gpio pin number generic with actual pins used

parent 575cdee5
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Showing with 12 additions and 9 deletions
general-cores @ 0ec5f930
Subproject commit 1c3e17ab09f37a643455bb0114b342e5b2db0947
Subproject commit 0ec5f930ebab450f86d1be4edbbae56d751bd5ad
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ e44d45dc
......@@ -144,7 +144,7 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 32;
constant c_NUM_GPIO_PINS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 7;
constant c_SLAVE_DPRAM : integer := 0;
......@@ -349,7 +349,7 @@ begin -- rtl
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => 32,
g_num_pins => c_NUM_GPIO_PINS,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys_i,
......
top/bare_top/scb_top_bare.vhd
View file @ e44d45dc
......@@ -152,6 +152,7 @@ architecture rtl of scb_top_bare is
constant c_TRU_EVENTS : integer := 1;
constant c_ALL_EVENTS : integer := c_TRU_EVENTS + c_RTU_EVENTS + c_epevents_sz;
constant c_DUMMY_RMON : boolean := false; -- define TRUE to enable dummy_rmon module for debugging PSTAT
constant c_NUM_GPIO_PINS : integer := 1;
-- constant c_epevents_sz : integer := 15;
-------------------------------------------------------------------------------
-- Interconnect & memory layout
......@@ -282,7 +283,6 @@ architecture rtl of scb_top_bare is
signal txtsu_timestamps_ack : std_logic_vector(c_NUM_PORTS-1 downto 0);
signal txtsu_timestamps : t_txtsu_timestamp_array(c_NUM_PORTS-1 downto 0);
signal dummy : std_logic_vector(31 downto 0);
signal tru_enabled : std_logic;
-- PSTAT: RMON counters
......@@ -358,7 +358,9 @@ architecture rtl of scb_top_bare is
TRIG3 : in std_logic_vector(31 downto 0));
end component;
signal gpio_out : std_logic_vector(31 downto 0);
signal gpio_out : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
signal gpio_in : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
signal dummy : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
-----------------------------------------------------------------------------
-- TRU stuff
......@@ -897,7 +899,7 @@ begin
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => 32,
g_num_pins => c_NUM_GPIO_PINS,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys,
......@@ -906,12 +908,13 @@ begin
slave_o => cnx_master_in(c_SLAVE_GPIO),
gpio_b => dummy,
gpio_out_o => gpio_out,
gpio_in_i => gpio_i);
gpio_in_i => gpio_in);
uart_sel_o <= gpio_out(31);
uart_sel_o <= gpio_out(0);
gpio_o <= gpio_out;
gpio_o(0) <= gpio_out(0);
gpio_in(0) <= gpio_i(0);
U_MiniBackplane_I2C0 : xwb_i2c_master
generic map (
......
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