swcore_pll to generate clock for switching core

e5899d52 · Grzegorz Daniluk · f39a7d58 · e5899d52 · e5899d52 · e5899d52
Commit e5899d52 authored Feb 17, 2014 by Grzegorz Daniluk
4 changed files
--- a/top/scb_8ports/Manifest.py
+++ b/top/scb_8ports/Manifest.py
-files = ["scb_top_synthesis.ucf", "scb_top_synthesis.vhd"];
+files = ["scb_top_synthesis.ucf", "scb_top_synthesis.vhd", "swcore_pll.vhd"];

 modules = { "local" : [ "../../", "../bare_top"  ] };


--- a/top/scb_8ports/scb_top_synthesis.ucf
+++ b/top/scb_8ports/scb_top_synthesis.ucf
@@ -360,3 +360,6 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
 TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;

 #NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE; 
+#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
+TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -156,6 +156,18 @@ end scb_top_synthesis;

 architecture Behavioral of scb_top_synthesis is

+
+  component swcore_pll is
+   port
+   (-- Clock in ports
+    clk_sys_i           : in     std_logic;
+    -- Clock out ports
+    clk_aux_o          : out    std_logic
+   );
+  end component;
+
+
+
  constant c_NUM_PHYS  : integer := 8;
  constant c_NUM_PORTS : integer := 8;

@@ -211,6 +223,7 @@ architecture Behavioral of scb_top_synthesis is
  signal clk_gtx8_11  : std_logic;
  signal clk_gtx12_15 : std_logic;
  signal clk_gtx16_19 : std_logic;
+  signal clk_aux_unused : std_logic;

  signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);

@@ -412,7 +425,8 @@ begin
      DIFF_TERM  => true,
      IOSTANDARD => "LVDS_25")
    port map (
-      O  => clk_aux,
+      --O  => clk_aux,
+      O  => clk_aux_unused,
      I  => fpga_clk_aux_p_i,
      IB => fpga_clk_aux_n_i);

@@ -426,7 +440,8 @@ begin
      I  => fpga_clk_dmtd_p_i,
      IB => fpga_clk_dmtd_n_i);

-  
+  U_swcore_pll: swcore_pll port map  ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
+
  U_SYS_PLL : PLL_BASE
    generic map (
      BANDWIDTH          => "OPTIMIZED",

--- a/top/scb_8ports/swcore_pll.vhd
+++ b/top/scb_8ports/swcore_pll.vhd
+-- file: swcore_pll.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___187.500______0.000______50.0______266.979____459.961
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary____________62.5____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity swcore_pll is
+port
+ (-- Clock in ports
+  clk_sys_i           : in     std_logic;
+  -- Clock out ports
+  clk_aux_o          : out    std_logic
+ );
+end swcore_pll;
+
+architecture xilinx of swcore_pll is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "swcore_pll,clk_wiz_v4_1,{component_name=swcore_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=16.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1_unused   : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2_unused   : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3_unused   : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal locked_unused    : std_logic;
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : BUFG
+  port map
+   (O => clkin1,
+    I => clk_sys_i);
+
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+  mmcm_adv_inst : MMCM_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    CLOCK_HOLD           => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => 4,
+    CLKFBOUT_MULT_F      => 61.000,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => 8.000,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => 16.000,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1_unused,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2_unused,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3_unused,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => locked_unused,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => '0');
+
+  -- Output buffering
+  -------------------------------------
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => clk_aux_o,
+    I   => clkout0);
+
+
+
+end xilinx;