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White Rabbit Switch - Gateware
Commit e6e3ac2d authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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add more generics to configure top module

parent 5061de36
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Showing with 50 additions and 25 deletions
top/bare_top/scb_top_bare.vhd
View file @ e6e3ac2d
......@@ -28,7 +28,9 @@ entity scb_top_bare is
g_with_TATSU : boolean := false;
g_with_HWDU : boolean := false;
g_with_HWIU : boolean := false;
g_with_PSTATS : boolean := true
g_with_PSTATS : boolean := true;
g_with_muxed_CS : boolean := false;
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0')
);
port (
sys_rst_n_i : in std_logic; -- global reset
......@@ -228,6 +230,15 @@ architecture rtl of scb_top_bare is
end if;
end f_bool2int;
function f_logic2bool(x : std_logic) return boolean is
begin
if(x = '1') then
return true;
else
return false;
end if;
end f_logic2bool;
constant c_cnx_endpoint_addr : t_wishbone_address_array(c_MAX_PORTS-1 downto 0) :=
f_gen_endpoint_addresses;
constant c_cnx_endpoint_mask : t_wishbone_address_array(c_MAX_PORTS-1 downto 0) :=
......@@ -590,7 +601,7 @@ begin
g_with_rtu => true,
g_with_leds => true,
g_with_dmtd => false,
g_with_packet_injection => true,
g_with_packet_injection => f_logic2bool(g_inj_per_EP(i)),
g_use_new_rxcrc => true,
g_use_new_txcrc => true)
port map (
......@@ -1056,24 +1067,24 @@ begin
clk_sys_o <= clk_sys;
--
-- CS_ICON : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
-- CS_ILA : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_sys, --phys_i(0).rx_clk,
-- TRIG0 => T0,
-- TRIG1 => T1,
-- TRIG2 => T2,
-- TRIG3 => T3);
--
-- T0 <= TRIG0(to_integer(unsigned(dbg_chps_id)));
-- T1 <= TRIG1(to_integer(unsigned(dbg_chps_id)));
-- T2 <= TRIG2(to_integer(unsigned(dbg_chps_id)));
-- T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
gen_muxed_CS: if g_with_muxed_CS = true generate
CS_ICON : chipscope_icon
port map (
CONTROL0 => CONTROL0);
CS_ILA : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys, --phys_i(0).rx_clk,
TRIG0 => T0,
TRIG1 => T1,
TRIG2 => T2,
TRIG3 => T3);
T0 <= TRIG0(to_integer(unsigned(dbg_chps_id)));
T1 <= TRIG1(to_integer(unsigned(dbg_chps_id)));
T2 <= TRIG2(to_integer(unsigned(dbg_chps_id)));
T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
end generate;
----------------------------- dbg_id0
TRIG0(0)(15 downto 0) <= phys_i(0).rx_data;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ e6e3ac2d
......@@ -225,7 +225,10 @@ package wrsw_top_pkg is
g_with_TRU : boolean := false;
g_with_TATSU : boolean := false;
g_with_HWDU : boolean := false;
g_with_HWIU : boolean := false);
g_with_HWIU : boolean := false;
g_with_PSTATS : boolean := true;
g_with_muxed_CS : boolean := false;
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0'));
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ e6e3ac2d
......@@ -239,7 +239,9 @@ architecture Behavioral of scb_top_synthesis is
g_with_TRU : boolean;
g_with_TATSU : boolean;
g_with_HWDU : boolean;
g_with_PSTATS : boolean);
g_with_PSTATS : boolean;
g_with_muxed_CS : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0));
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -598,7 +600,9 @@ begin
g_with_TRU => false,
g_with_TATSU => false,
g_with_HWDU => true,
g_with_PSTATS => false)
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_inj_per_EP => "00" & x"0003") --only first two ports have injection engine
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ e6e3ac2d
......@@ -240,7 +240,10 @@ architecture Behavioral of scb_top_synthesis is
g_with_TRU : boolean;
g_with_TATSU : boolean;
g_with_HWDU : boolean;
g_with_HWIU : boolean);
g_with_HWIU : boolean;
g_with_PSTATS : boolean;
g_with_muxed_CS : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0));
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -599,7 +602,11 @@ begin
g_with_TRU => true,
g_with_TATSU => true,
g_with_HWDU => false,
g_with_HWIU => true)
g_with_HWIU => true,
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_inj_per_EP => "00" & x"0003" --only first two ports have injection engine
)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
......
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