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White Rabbit Switch - Gateware
Commit e6f4719b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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modules/wrsw_rtu: (up to) 32-port version, not tested in HW

parent 7ab86397
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Showing with 1224 additions and 817 deletions
modules/wrsw_rtu/Manifest.py
View file @ e6f4719b
files = [
"global_defs.vhd",
"rtu_lookup_engine.vhd",
"wrsw_rr_arbiter.vhd",
"wrsw_rtu_crc_pkg.vhd",
"wrsw_rtu_match.vhd",
"wrsw_rtu_private_pkg.vhd",
"PCK_CRC16_D16.vhd",
"showahead_fifo.vhd",
"wrsw_rtu_components_pkg.vhd",
"wrsw_rtu_crc.vhd",
"wrsw_rtu_port.vhd",
"rtu_lookup_engine.vhd",
"rtu_rr_arbiter.vhd",
"rtu_crc_pkg.vhd",
"rtu_match.vhd",
"rtu_private_pkg.vhd",
"rtu_components_pkg.vhd",
"rtu_crc.vhd",
"rtu_port.vhd",
"wrsw_rtu.vhd",
"xwrsw_rtu.vhd",
"rtu_wishbone_slave.vhd",
"rtu_wbgen2_pkg.vhd"
"rtu_wbgen2_pkg.vhd",
"pack_unpack_pkg.vhd"
]
\ No newline at end of file
modules/wrsw_rtu/wrsw_rtu_crc.vhd → modules/wrsw_rtu/rtu_crc.vhd
View file @ e6f4719b
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-12
-- Last update: 2012-01-25
-- Last update: 2012-06-22
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -43,13 +43,13 @@ library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wrsw_rtu_crc_pkg.all;
use work.wrsw_rtu_private_pkg.all;
use work.rtu_crc_pkg.all;
use work.rtu_private_pkg.all;
entity wrsw_rtu_crc is
entity rtu_crc is
port (
mac_addr_i : in std_logic_vector(c_wrsw_mac_addr_width - 1 downto 0);
fid_i : in std_logic_vector(c_wrsw_fid_width - 1 downto 0);
......@@ -57,7 +57,8 @@ entity wrsw_rtu_crc is
hash_o : out std_logic_vector(c_wrsw_hash_width - 1 downto 0)
);
end entity;
architecture behavior of wrsw_rtu_crc is
architecture behavior of rtu_crc is
signal s_crc16 : std_logic_vector(15 downto 0);
signal s_fid : std_logic_vector(15 downto 0);
begin
......
modules/wrsw_rtu/wrsw_rtu_crc_pkg.vhd → modules/wrsw_rtu/rtu_crc_pkg.vhd
View file @ e6f4719b
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-12
-- Last update: 2010-05-12
-- Last update: 2012-06-22
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -54,7 +54,7 @@ library work;
use work.PCK_CRC16_D16.all;
package wrsw_rtu_crc_pkg is
package rtu_crc_pkg is
function crc16_ccitt
(mac_addr_i: std_logic_vector(47 downto 0);
......@@ -72,10 +72,10 @@ package wrsw_rtu_crc_pkg is
return std_logic_vector;
end wrsw_rtu_crc_pkg;
end rtu_crc_pkg;
package body wrsw_rtu_crc_pkg is
package body rtu_crc_pkg is
function crc16_ccitt
(mac_addr_i: std_logic_vector(47 downto 0);
......@@ -178,4 +178,4 @@ package body wrsw_rtu_crc_pkg is
return v_hash_o;
end crc16_dect;
end wrsw_rtu_crc_pkg;
\ No newline at end of file
end rtu_crc_pkg;
modules/wrsw_rtu/rtu_lookup_engine.vhd
View file @ e6f4719b
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-22
-- Last update: 2012-04-26
-- Last update: 2012-06-22
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -43,7 +43,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wrsw_rtu_private_pkg.all;
use work.rtu_private_pkg.all;
use work.genram_pkg.all;
......@@ -179,7 +179,7 @@ begin
end if;
end process;
cur_entry <= f_unmarshall_htab_entry(mem_out(0), mem_out(1), mem_out(2), mem_out(3));
cur_entry <= f_unmarshall_htab_entry(mem_out(0), mem_out(1), mem_out(2), mem_out(3), mem_out(4));
cur_entry.bucket_entry <= std_logic_vector(bucket_entry_d0);
p_match : process(clk_match_i)
......
modules/wrsw_rtu/wrsw_rr_arbiter.vhd → modules/wrsw_rtu/rtu_rr_arbiter.vhd
View file @ e6f4719b
......@@ -49,10 +49,10 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wrsw_rtu_private_pkg.all;
use work.rtu_private_pkg.all;
entity wrsw_rr_arbiter is
entity rtu_rr_arbiter is
generic (
g_width : natural :=4 );
port (
......@@ -62,7 +62,7 @@ entity wrsw_rr_arbiter is
);
end entity;
architecture behavior of wrsw_rr_arbiter is
architecture behavior of rtu_rr_arbiter is
----------------Internal Registers-----------------
signal s_reqs :std_logic_vector(g_width - 1 downto 0);
......
modules/wrsw_rtu/rtu_wbgen2_pkg.vhd
View file @ e6f4719b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : rtu_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from rtu_wishbone_slave.wb
-- Created : Mon Mar 12 01:43:29 2012
-- Created : Mon Jun 25 14:23:30 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_wishbone_slave.wb
......@@ -36,7 +36,7 @@ package rtu_wbgen2_pkg is
ufifo_smac_hi_i : std_logic_vector(15 downto 0);
ufifo_vid_i : std_logic_vector(11 downto 0);
ufifo_prio_i : std_logic_vector(2 downto 0);
ufifo_pid_i : std_logic_vector(3 downto 0);
ufifo_pid_i : std_logic_vector(7 downto 0);
ufifo_has_vid_i : std_logic;
ufifo_has_prio_i : std_logic;
mfifo_rd_req_i : std_logic;
......@@ -84,6 +84,14 @@ package rtu_wbgen2_pkg is
pcr_prio_val_load_o : std_logic;
pcr_b_unrec_o : std_logic;
pcr_b_unrec_load_o : std_logic;
vtr1_vid_o : std_logic_vector(11 downto 0);
vtr1_fid_o : std_logic_vector(7 downto 0);
vtr1_drop_o : std_logic;
vtr1_has_prio_o : std_logic;
vtr1_prio_override_o : std_logic;
vtr1_prio_o : std_logic_vector(2 downto 0);
vtr1_update_o : std_logic;
vtr2_port_mask_o : std_logic_vector(31 downto 0);
ufifo_wr_full_o : std_logic;
ufifo_wr_empty_o : std_logic;
mfifo_rd_empty_o : std_logic;
......@@ -110,6 +118,14 @@ package rtu_wbgen2_pkg is
pcr_prio_val_load_o => '0',
pcr_b_unrec_o => '0',
pcr_b_unrec_load_o => '0',
vtr1_vid_o => (others => '0'),
vtr1_fid_o => (others => '0'),
vtr1_drop_o => '0',
vtr1_has_prio_o => '0',
vtr1_prio_override_o => '0',
vtr1_prio_o => (others => '0'),
vtr1_update_o => '0',
vtr2_port_mask_o => (others => '0'),
ufifo_wr_full_o => '0',
ufifo_wr_empty_o => '0',
mfifo_rd_empty_o => '0',
......
modules/wrsw_rtu/rtu_wishbone_slave.vhd
View file @ e6f4719b
This diff is collapsed.
modules/wrsw_rtu/rtu_wishbone_slave.wb
View file @ e6f4719b
......@@ -174,6 +174,88 @@ peripheral {
};
};
reg {
name = "VLAN Table Register 1";
prefix = "VTR1";
field {
prefix = "VID";
name = "VLAN ID";
size = 12;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "FID";
name = "Filtering Database ID";
description = "Assigns the VID to a particular filtering database";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "DROP";
name = "Drop";
description = "1: drop all packets belonging to this VLAN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "HAS_PRIO";
name = "Has user-defined priority";
description = "1: VLAN has user-defined priority";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "PRIO_OVERRIDE";
name = "Override endpoint-assigned priority";
description = "1: always take the priority from the PRIO field, regardless of the priority value assigned at the endpoint. ";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "PRIO";
name = "Priority value";
type = SLV;
size = 3;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "UPDATE";
name = "Force VLAN table entry update";
description = "write 1: flush VTR1 and VTR2 registers to VLAN table entry designated in VTR1.VID";
type = MONOSTABLE;
}
};
reg {
prefix = "VTR2";
name = "VLAN Table Register 2";
field {
name = "Port Mask";
prefix = "PORT_MASK";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
irq {
name = "UFIFO Not Empty IRQ";
description = "Interrupt active when there are some requests in UFIFO.";
......@@ -255,8 +337,8 @@ peripheral {
name = "Port ID";
description = "Identifier of RTU port to which came the request.";
prefix = "PID";
size = 4;
align = 4;
size = 8;
align = 8;
type = SLV;
};
......@@ -280,6 +362,7 @@ peripheral {
};
};
ram {
name = "Aging bitmap for main hashtable";
description = "Each bit in this memory reflects the state of corresponding entry in main hashtable:\
......@@ -298,21 +381,6 @@ peripheral {
};
ram {
name = "VLAN table (VLAN_TAB)";
description = "It stores VLAN-related information identified by VLAN ID (VID)";
prefix = "VLAN_TAB";
width = 32;
size = 4096 ; -- 4096 entries as defined in 802.1Q-2005, page 12
access_dev = READ_ONLY;
access_bus = READ_WRITE;
-- --[changed 6/10/2010] clock = "clk_match_i";
--clock = "clk_match_i"; --async?
};
fifo_reg {
name = "Main hashtable CPU access FIFO (MFIFO)";
......
modules/wrsw_rtu/wrsw_rtu.vhd
View file @ e6f4719b
This diff is collapsed.
modules/wrsw_rtu/xwrsw_rtu.vhd
View file @ e6f4719b
......@@ -6,7 +6,7 @@
-- Authors : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2012-01-10
-- Last update: 2012-03-06
-- Last update: 2012-06-25
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -45,7 +45,7 @@ use ieee.math_real.log2;
use work.wishbone_pkg.all;
use work.wrsw_shared_types_pkg.all;
use work.wrsw_rtu_private_pkg.all;
use work.rtu_private_pkg.all;
entity xwrsw_rtu is
......@@ -74,59 +74,61 @@ entity xwrsw_rtu is
end xwrsw_rtu;
architecture wrapper of xwrsw_rtu is
component wrsw_rtu
generic (
g_num_ports : integer);
port (
clk_sys_i : in std_logic;
clk_match_i : in std_logic;
rst_n_i : in std_logic;
rtu_idle_o : out std_logic_vector(c_rtu_num_ports-1 downto 0);
rq_strobe_p_i : in std_logic_vector(c_rtu_num_ports-1 downto 0);
rq_smac_i : in std_logic_vector(c_wrsw_mac_addr_width * c_rtu_num_ports - 1 downto 0);
rq_dmac_i : in std_logic_vector(c_wrsw_mac_addr_width * c_rtu_num_ports -1 downto 0);
rq_vid_i : in std_logic_vector(c_wrsw_vid_width * c_rtu_num_ports - 1 downto 0);
rq_has_vid_i : in std_logic_vector(c_rtu_num_ports -1 downto 0);
rq_prio_i : in std_logic_vector(c_wrsw_prio_width * c_rtu_num_ports -1 downto 0);
rq_has_prio_i : in std_logic_vector(c_rtu_num_ports -1 downto 0);
rsp_valid_o : out std_logic_vector (c_rtu_num_ports-1 downto 0);
rsp_dst_port_mask_o : out std_logic_vector(c_wrsw_num_ports * c_rtu_num_ports - 1 downto 0);
rsp_drop_o : out std_logic_vector(c_rtu_num_ports -1 downto 0);
rsp_prio_o : out std_logic_vector (c_rtu_num_ports * c_wrsw_prio_width-1 downto 0);
rsp_ack_i : in std_logic_vector(c_rtu_num_ports -1 downto 0);
port_almost_full_o : out std_logic_vector(c_rtu_num_ports -1 downto 0);
port_full_o : out std_logic_vector(c_rtu_num_ports -1 downto 0);
wb_addr_i : in std_logic_vector(13 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
rtu_idle_o : out std_logic_vector(g_num_ports-1 downto 0);
rq_strobe_p_i : in std_logic_vector(g_num_ports-1 downto 0);
rq_smac_i : in std_logic_vector(c_wrsw_mac_addr_width * g_num_ports - 1 downto 0);
rq_dmac_i : in std_logic_vector(c_wrsw_mac_addr_width * g_num_ports -1 downto 0);
rq_vid_i : in std_logic_vector(c_wrsw_vid_width * g_num_ports - 1 downto 0);
rq_has_vid_i : in std_logic_vector(g_num_ports -1 downto 0);
rq_prio_i : in std_logic_vector(c_wrsw_prio_width * g_num_ports -1 downto 0);
rq_has_prio_i : in std_logic_vector(g_num_ports -1 downto 0);
rsp_valid_o : out std_logic_vector (g_num_ports-1 downto 0);
rsp_dst_port_mask_o : out std_logic_vector(c_rtu_max_ports * g_num_ports - 1 downto 0);
rsp_drop_o : out std_logic_vector(g_num_ports -1 downto 0);
rsp_prio_o : out std_logic_vector (g_num_ports * c_wrsw_prio_width-1 downto 0);
rsp_ack_i : in std_logic_vector(g_num_ports -1 downto 0);
port_almost_full_o : out std_logic_vector(g_num_ports -1 downto 0);
port_full_o : out std_logic_vector(g_num_ports -1 downto 0);
wb_adr_i : in std_logic_vector(13 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
wb_we_i : in std_logic);
wb_we_i : in std_logic;
wb_stall_o : out std_logic);
end component;
constant c_prio_num_width : integer := integer(CEIL(LOG2(real(g_prio_num ))));
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal rq_strobe_p : std_logic_vector(c_rtu_num_ports-1 downto 0);
signal rq_smac : std_logic_vector(c_wrsw_mac_addr_width * c_rtu_num_ports - 1 downto 0);
signal rq_dmac : std_logic_vector(c_wrsw_mac_addr_width * c_rtu_num_ports -1 downto 0);
signal rq_vid : std_logic_vector(c_wrsw_vid_width * c_rtu_num_ports - 1 downto 0);
signal rq_has_vid : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal rq_prio : std_logic_vector(c_wrsw_prio_width * c_rtu_num_ports -1 downto 0);
signal rq_has_prio : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal rsp_valid : std_logic_vector (c_rtu_num_ports-1 downto 0);
signal rsp_dst_port_mask : std_logic_vector(c_wrsw_num_ports * c_rtu_num_ports - 1 downto 0);
signal rsp_drop : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal rsp_prio : std_logic_vector (c_rtu_num_ports * c_wrsw_prio_width-1 downto 0);
signal rsp_ack : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal port_full_hacked : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal port_full : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal port_idle : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal rq_strobe_p : std_logic_vector(g_num_ports-1 downto 0);
signal rq_smac : std_logic_vector(c_wrsw_mac_addr_width * g_num_ports - 1 downto 0);
signal rq_dmac : std_logic_vector(c_wrsw_mac_addr_width * g_num_ports -1 downto 0);
signal rq_vid : std_logic_vector(c_wrsw_vid_width * g_num_ports - 1 downto 0);
signal rq_has_vid : std_logic_vector(g_num_ports -1 downto 0);
signal rq_prio : std_logic_vector(c_wrsw_prio_width * g_num_ports -1 downto 0);
signal rq_has_prio : std_logic_vector(g_num_ports -1 downto 0);
signal rsp_valid : std_logic_vector (g_num_ports-1 downto 0);
signal rsp_dst_port_mask : std_logic_vector(g_num_ports * c_rtu_max_ports - 1 downto 0);
signal rsp_drop : std_logic_vector(g_num_ports -1 downto 0);
signal rsp_prio : std_logic_vector (g_num_ports * c_wrsw_prio_width-1 downto 0);
signal rsp_ack : std_logic_vector(g_num_ports -1 downto 0);
signal port_full_hacked : std_logic_vector(g_num_ports -1 downto 0);
signal port_full : std_logic_vector(g_num_ports -1 downto 0);
signal port_idle : std_logic_vector(g_num_ports -1 downto 0);
begin -- wrapper
......@@ -140,7 +142,7 @@ begin -- wrapper
rq_has_vid(i) <= req_i(i).has_vid;
rsp_o(i).valid <= rsp_valid(i);
rsp_o(i).port_mask(g_port_mask_bits-1 downto 0) <= rsp_dst_port_mask(c_wrsw_num_ports * i + g_port_mask_bits -1 downto c_wrsw_num_ports * i);
rsp_o(i).port_mask(c_rtu_max_ports-1 downto 0) <= rsp_dst_port_mask(c_rtu_max_ports * (i+1) -1 downto c_rtu_max_ports * i);
rsp_o(i).drop <= rsp_drop(i);
rsp_ack(i) <= rsp_ack_i(i);
rsp_o(i).prio <= rsp_prio(c_wrsw_prio_width*i + c_prio_num_width-1 downto c_wrsw_prio_width*i);
......@@ -180,7 +182,7 @@ begin -- wrapper
end generate gen_hack_f;
--------------------------------------------------------------------------------------------------
gen_term_unused : for i in g_num_ports to c_rtu_num_ports-1 generate
gen_term_unused : for i in g_num_ports to g_num_ports-1 generate
rq_strobe_p(i) <= '0';
rsp_ack(i) <= '1';
end generate gen_term_unused;
......@@ -206,6 +208,9 @@ begin -- wrapper
U_Wrapped_RTU : wrsw_rtu
generic map (
g_num_ports => g_num_ports)
port map (
clk_sys_i => clk_sys_i,
clk_match_i => clk_sys_i,
......@@ -224,9 +229,9 @@ begin -- wrapper
rsp_prio_o => rsp_prio,
rsp_ack_i => rsp_ack,
port_full_o => port_full,
wb_addr_i => wb_in.adr(13 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_adr_i => wb_in.adr(13 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_sel_i => wb_in.sel,
wb_cyc_i => wb_in.cyc,
wb_stb_i => wb_in.stb,
......
sim/regs/rtu_regs.vh
View file @ e6f4719b
`define ADDR_RTU_GCR 16'h0
`define ADDR_RTU_GCR 11'h0
`define RTU_GCR_G_ENA_OFFSET 0
`define RTU_GCR_G_ENA 32'h00000001
`define RTU_GCR_MFIFOTRIG_OFFSET 1
`define RTU_GCR_MFIFOTRIG 32'h00000002
`define RTU_GCR_POLY_VAL_OFFSET 8
`define RTU_GCR_POLY_VAL 32'h00ffff00
`define ADDR_RTU_PSR 16'h4
`define ADDR_RTU_PSR 11'h4
`define RTU_PSR_PORT_SEL_OFFSET 0
`define RTU_PSR_PORT_SEL 32'h000000ff
`define RTU_PSR_N_PORTS_OFFSET 8
`define RTU_PSR_N_PORTS 32'h0000ff00
`define ADDR_RTU_PCR 16'h8
`define ADDR_RTU_PCR 11'h8
`define RTU_PCR_LEARN_EN_OFFSET 0
`define RTU_PCR_LEARN_EN 32'h00000001
`define RTU_PCR_PASS_ALL_OFFSET 1
......@@ -23,60 +23,76 @@
`define RTU_PCR_PRIO_VAL 32'h00000070
`define RTU_PCR_B_UNREC_OFFSET 7
`define RTU_PCR_B_UNREC 32'h00000080
`define ADDR_RTU_EIC_IDR 16'h20
`define ADDR_RTU_VTR1 11'hc
`define RTU_VTR1_VID_OFFSET 0
`define RTU_VTR1_VID 32'h00000fff
`define RTU_VTR1_FID_OFFSET 12
`define RTU_VTR1_FID 32'h000ff000
`define RTU_VTR1_DROP_OFFSET 20
`define RTU_VTR1_DROP 32'h00100000
`define RTU_VTR1_HAS_PRIO_OFFSET 21
`define RTU_VTR1_HAS_PRIO 32'h00200000
`define RTU_VTR1_PRIO_OVERRIDE_OFFSET 22
`define RTU_VTR1_PRIO_OVERRIDE 32'h00400000
`define RTU_VTR1_PRIO_OFFSET 23
`define RTU_VTR1_PRIO 32'h03800000
`define RTU_VTR1_UPDATE_OFFSET 26
`define RTU_VTR1_UPDATE 32'h04000000
`define ADDR_RTU_VTR2 11'h10
`define RTU_VTR2_PORT_MASK_OFFSET 0
`define RTU_VTR2_PORT_MASK 32'hffffffff
`define ADDR_RTU_EIC_IDR 11'h20
`define RTU_EIC_IDR_NEMPTY_OFFSET 0
`define RTU_EIC_IDR_NEMPTY 32'h00000001
`define ADDR_RTU_EIC_IER 16'h24
`define ADDR_RTU_EIC_IER 11'h24
`define RTU_EIC_IER_NEMPTY_OFFSET 0
`define RTU_EIC_IER_NEMPTY 32'h00000001
`define ADDR_RTU_EIC_IMR 16'h28
`define ADDR_RTU_EIC_IMR 11'h28
`define RTU_EIC_IMR_NEMPTY_OFFSET 0
`define RTU_EIC_IMR_NEMPTY 32'h00000001
`define ADDR_RTU_EIC_ISR 16'h2c
`define ADDR_RTU_EIC_ISR 11'h2c
`define RTU_EIC_ISR_NEMPTY_OFFSET 0
`define RTU_EIC_ISR_NEMPTY 32'h00000001
`define ADDR_RTU_UFIFO_R0 16'h30
`define ADDR_RTU_UFIFO_R0 11'h30
`define RTU_UFIFO_R0_DMAC_LO_OFFSET 0
`define RTU_UFIFO_R0_DMAC_LO 32'hffffffff
`define ADDR_RTU_UFIFO_R1 16'h34
`define ADDR_RTU_UFIFO_R1 11'h34
`define RTU_UFIFO_R1_DMAC_HI_OFFSET 0
`define RTU_UFIFO_R1_DMAC_HI 32'h0000ffff
`define ADDR_RTU_UFIFO_R2 16'h38
`define ADDR_RTU_UFIFO_R2 11'h38
`define RTU_UFIFO_R2_SMAC_LO_OFFSET 0
`define RTU_UFIFO_R2_SMAC_LO 32'hffffffff
`define ADDR_RTU_UFIFO_R3 16'h3c
`define ADDR_RTU_UFIFO_R3 11'h3c
`define RTU_UFIFO_R3_SMAC_HI_OFFSET 0
`define RTU_UFIFO_R3_SMAC_HI 32'h0000ffff
`define ADDR_RTU_UFIFO_R4 16'h40
`define ADDR_RTU_UFIFO_R4 11'h40
`define RTU_UFIFO_R4_VID_OFFSET 0
`define RTU_UFIFO_R4_VID 32'h00000fff
`define RTU_UFIFO_R4_PRIO_OFFSET 12
`define RTU_UFIFO_R4_PRIO 32'h00007000
`define RTU_UFIFO_R4_PID_OFFSET 16
`define RTU_UFIFO_R4_PID 32'h000f0000
`define RTU_UFIFO_R4_HAS_VID_OFFSET 20
`define RTU_UFIFO_R4_HAS_VID 32'h00100000
`define RTU_UFIFO_R4_HAS_PRIO_OFFSET 21
`define RTU_UFIFO_R4_HAS_PRIO 32'h00200000
`define ADDR_RTU_UFIFO_CSR 16'h44
`define RTU_UFIFO_R4_PID 32'h00ff0000
`define RTU_UFIFO_R4_HAS_VID_OFFSET 24
`define RTU_UFIFO_R4_HAS_VID 32'h01000000
`define RTU_UFIFO_R4_HAS_PRIO_OFFSET 25
`define RTU_UFIFO_R4_HAS_PRIO 32'h02000000
`define ADDR_RTU_UFIFO_CSR 11'h44
`define RTU_UFIFO_CSR_EMPTY_OFFSET 17
`define RTU_UFIFO_CSR_EMPTY 32'h00020000
`define RTU_UFIFO_CSR_USEDW_OFFSET 0
`define RTU_UFIFO_CSR_USEDW 32'h0000007f
`define ADDR_RTU_MFIFO_R0 16'h48
`define ADDR_RTU_MFIFO_R0 11'h48
`define RTU_MFIFO_R0_AD_SEL_OFFSET 0
`define RTU_MFIFO_R0_AD_SEL 32'h00000001
`define ADDR_RTU_MFIFO_R1 16'h4c
`define ADDR_RTU_MFIFO_R1 11'h4c
`define RTU_MFIFO_R1_AD_VAL_OFFSET 0
`define RTU_MFIFO_R1_AD_VAL 32'hffffffff
`define ADDR_RTU_MFIFO_CSR 16'h50
`define ADDR_RTU_MFIFO_CSR 11'h50
`define RTU_MFIFO_CSR_FULL_OFFSET 16
`define RTU_MFIFO_CSR_FULL 32'h00010000
`define RTU_MFIFO_CSR_EMPTY_OFFSET 17
`define RTU_MFIFO_CSR_EMPTY 32'h00020000
`define RTU_MFIFO_CSR_USEDW_OFFSET 0
`define RTU_MFIFO_CSR_USEDW 32'h0000003f
`define BASE_RTU_ARAM 16'h4000
`define BASE_RTU_ARAM 11'h400
`define SIZE_RTU_ARAM 32'h100
`define BASE_RTU_VLAN_TAB 16'h8000
`define SIZE_RTU_VLAN_TAB 32'h1000
sim/simdrv_rtu.sv
View file @ e6f4719b
......@@ -177,7 +177,10 @@ task CRTUSimDriver::htab_write(int hash, int bucket, rtu_filtering_entry_t ent);
(('hFFFF & ent.port_mask_dst) << 16) |
(('hFFFF & ent.port_mask_src) ) ;
d[4] = 0;
d[4] =
(('hFFFF & (ent.port_mask_dst >> 16)) << 16) |
(('hFFFF & (ent.port_mask_src >> 16)) ) ;
mfifo_write(hash * 8 * 4 + bucket * 8, 5, d);
......@@ -278,17 +281,20 @@ task CRTUSimDriver::add_static_rule(bit[7:0] dmac[], bit[31:0] dpm);
endtask // CRTUSimDriver
task CRTUSimDriver::add_vlan_entry(int vlan_id, rtu_vlan_entry_t ent);
bit[31:0] val;
val = (('h1 & ent.drop) << 31) |
(('h1 & ent.prio_override) << 30) |
(('h7 & ent.prio) << 27) |
(('h1 & ent.has_prio) << 26) |
(('hFF & ent.fid) << 16) |
(('hFFFF & ent.port_mask) ) ;
uint64_t vtr1, vtr2;
vtr2 = ent.port_mask;
vtr1 = `RTU_VTR1_UPDATE
| (ent.drop ? `RTU_VTR1_DROP : 0)
| (ent.prio_override ? `RTU_VTR1_PRIO_OVERRIDE : 0)
| (ent.has_prio ? `RTU_VTR1_HAS_PRIO : 0)
| ((ent.prio & 'h7) << `RTU_VTR1_PRIO_OFFSET)
| ((ent.fid & 'hff) << `RTU_VTR1_FID_OFFSET);
bus.write(base_addr + `ADDR_RTU_VTR2, vtr2);
bus.write(base_addr + `ADDR_RTU_VTR1, vtr1);
bus.write(base_addr + `BASE_RTU_VLAN_TAB + (vlan_id * 4), val);
bus.write(base_addr + `BASE_RTU_VLAN_TAB + (vlan_id * 4), val);
endtask // CRTUSimDriver
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