rudimentary testbench for the RISC-V RT subsys

f0137c5c · Tomasz Wlostowski · 5c2f1c1f · f0137c5c · f0137c5c · f0137c5c
Commit f0137c5c authored Nov 28, 2023 by Tomasz Wlostowski
5 changed files
--- a/testbench/wrsw_rt_subsystem/bus_device.svh
+++ b/testbench/wrsw_rt_subsystem/bus_device.svh
+//------------------------------------------------------------------------------
+// CERN BE-CEM-EDL
+// General Cores Library
+// https://www.ohwr.org/projects/general-cores
+//------------------------------------------------------------------------------
+//
+// units: gencores_sim_pkg
+//
+// description: Shared classes and interfaces for the gencores SV simulations
+//
+//------------------------------------------------------------------------------
+// Copyright CERN 2010-2019
+//------------------------------------------------------------------------------
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 2.0 (the "License"); you may not use this file except
+// in compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-2.0.
+// Unless required by applicable law or agreed to in writing, software,
+// hardware and materials distributed under this License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+// or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//------------------------------------------------------------------------------
+
+  `include "simdrv_defs.svh"
+
+    
+  class CBusDevice;
+    protected CBusAccessor m_acc;
+    protected uint64_t m_base;
+
+    function new(CBusAccessor acc, uint64_t base);
+      m_acc  = acc;
+      m_base = base;
+    endfunction  // new
+
+    virtual task automatic writel(uint32_t addr, uint32_t val);
+      m_acc.write(m_base + addr, val);
+    endtask  // writel
+
+
+    virtual task automatic readl(uint32_t addr, output uint32_t val);
+      automatic uint64_t val64;
+      m_acc.read(m_base + addr, val64);
+      val = val64;
+    endtask  // readl
+
+
+  virtual task automatic set_bits(uint32_t addr, uint32_t bits);
+    uint32_t r;
+    readl(addr, r);
+    r |= bits;
+    writel(addr, r);
+  endtask
+
+  virtual task automatic clear_bits(uint32_t addr, uint32_t bits);
+    uint32_t r;
+    readl(addr, r);
+    r &= ~bits;
+    writel(addr, r);
+  endtask
+
+  endclass  // CBusDevice
+
--- a/testbench/wrsw_rt_subsystem/main.sv
+++ b/testbench/wrsw_rt_subsystem/main.sv
+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "vhd_wishbone_master.svh"
+`include "bus_device.svh"
+
+`define WRS_BASE_RT_SUBSYSTEM 'h00000000
+`define WRS_RT_BASE_MAILBOX   'h00000000
+`define WRS_RT_BASE_URV_BOOT  'h00010900
+
+`define WRC_CPU_CSR_REG_RESET 'h00000000
+`define WRC_CPU_CSR_REG_UADDR 'h00000004
+`define WRC_CPU_CSR_REG_UDATA 'h00000008
+
+class RISCVLoader extends CBusDevice;
+  function new(CBusAccessor acc, uint64_t base);
+    super.new(acc, base);
+  endfunction
+  
+  task automatic load_binary( string filename );
+    int f = $fopen(filename,"rb");
+    int rv;
+    uint32_t uaddr = 0;
+    time t_start = $time;
+    $display("Loading %s", filename);
+    writel( `WRC_CPU_CSR_REG_RESET, 1 );
+    while( !$feof(f) )
+    begin
+      uint32_t udata;
+      rv = $fread(udata, f);
+      if (rv != 4 )
+        break;
+      writel( `WRC_CPU_CSR_REG_UADDR, uaddr );
+      writel( `WRC_CPU_CSR_REG_UDATA, udata );
+      uaddr++;
+    end
+
+    writel( `WRC_CPU_CSR_REG_RESET, 0 );
+
+    $display("CPU boot took %.0f us", real'($time - t_start) / real'(1us));
+
+    $fclose(f);
+  endtask
+
+endclass
+
+module main;
+    reg clk_sys = 0;
+    reg rst_sys_n = 0;
+
+ IVHDWishboneMaster
+  inst_sys_bus_master (
+    .clk_i(clk_sys),
+    .rst_n_i(rst_sys_n)
+  );
+
+
+    always #8ns clk_sys <= ~clk_sys;
+    initial begin
+        repeat(3) @(posedge clk_sys) ;
+        rst_sys_n <= 1;
+    end
+
+    
+scb_top_bare
+#(
+    .g_simulation(1'b1)
+) DUT (
+    .sys_rst_n_i(rst_sys_n),
+
+
+    //System clock 62.5 MHz
+    .clk_sys_i(clk_sys),
+    //62.5 MHz timing reference (from the AD9516 PLL output QDRII_CLK)
+    .clk_ref_i(clk_sys),
+
+    //62.5+ MHz DMTD offset clock (from the CDCM62001 PLL output DMTDCLK_MAIN)
+    .clk_dmtd_i(clk_sys),
+
+    //Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
+    //for re-phasing the 10 MHz input as well as clocking the 
+    .clk_aux_i(1'b0),
+
+	.clk_ext_mul_i	       (2'b00),
+	.clk_ext_mul_locked_i(1'b0),
+
+    .clk_aux_p_o (),
+    .clk_aux_n_o (),
+
+    .clk_500_o   (),
+
+    //Master wishbone bus (from the CPU bridge)
+    .cpu_wb_i   ( inst_sys_bus_master.out ),
+    .cpu_wb_o   ( inst_sys_bus_master.in ),
+    .cpu_irq_n_o(),
+
+    //Timing I/O
+
+    .pps_i       (1'b0),
+    .ppsin_term_o(),
+    .pps_o       (),
+
+    //DAC Drive
+    .dac_helper_load_o(),
+    .dac_helper_value_o(),
+    .dac_main_load_o(),
+    .dac_main_value_o(),
+   
+    //AD9516 PLL Control signals
+
+    .pll_status_i (1'b0),
+    .pll_mosi_o   (),
+    .pll_miso_i   (1'b0),
+    .pll_sck_o    (),
+    .pll_cs_n_o   (),
+    .pll_sync_n_o (),
+    .pll_reset_n_o(),
+
+    .uart_txd_o(),
+    .uart_rxd_i(1'b1),
+
+    //Low Jitter Daughterboard support
+    .ljd_dac_main_sync_n_o(),
+    .ljd_dac_main_sclk_o  (),
+    .ljd_dac_main_data_o  (),
+
+    //Misc pins
+
+    //GTX clock fanout enable
+    .clk_en_o(),
+
+    //GTX clock fanout source select
+    .clk_sel_o(),
+
+    //DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
+    .clk_dmtd_divsel_o(),
+
+    //UART source selection (FPGA/DBGU)
+    .uart_sel_o()
+
+
+    );
+
+    initial begin
+      CBusAccessor acc;
+      RISCVLoader loader;
+      uint64_t rv;
+      #1us;
+      acc = inst_sys_bus_master.get_accessor();
+      loader = new( acc, `WRS_BASE_RT_SUBSYSTEM + `WRS_RT_BASE_URV_BOOT );
+      $display("Loading...\n");
+      loader.load_binary("rt_cpu_v4.bin");
+
+      #100us; // give the CPU a while
+      acc.read( `WRS_BASE_RT_SUBSYSTEM + `WRS_RT_BASE_MAILBOX, rv );
+      $display("MBOX signature: %x", rv );
+      $stop;
+      
+    end
+
+
+endmodule
+
+
--- a/testbench/wrsw_rt_subsystem/rt_cpu_v4.bin
+++ b/testbench/wrsw_rt_subsystem/rt_cpu_v4.bin
--- a/testbench/wrsw_rt_subsystem/run.do
+++ b/testbench/wrsw_rt_subsystem/run.do
+vsim -L unisim -t 1ps work.main -voptargs="+acc"
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 600us
+wave zoomfull
+radix -hexadecimal
--- a/testbench/wrsw_rt_subsystem/wave.do
+++ b/testbench/wrsw_rt_subsystem/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -group top /main/DUT/sys_rst_n_i
+add wave -noupdate -group top /main/DUT/clk_sys_i
+add wave -noupdate -group top /main/DUT/clk_ref_i
+add wave -noupdate -group top /main/DUT/clk_dmtd_i
+add wave -noupdate -group top /main/DUT/clk_aux_i
+add wave -noupdate -group top /main/DUT/clk_ext_mul_i
+add wave -noupdate -group top /main/DUT/clk_ext_mul_locked_i
+add wave -noupdate -group top /main/DUT/clk_aux_p_o
+add wave -noupdate -group top /main/DUT/clk_aux_n_o
+add wave -noupdate -group top /main/DUT/clk_500_o
+add wave -noupdate -group top -expand /main/DUT/cpu_wb_i
+add wave -noupdate -group top /main/DUT/cpu_wb_o
+add wave -noupdate -group top /main/DUT/cpu_irq_n_o
+add wave -noupdate -group top /main/DUT/pps_i
+add wave -noupdate -group top /main/DUT/ppsin_term_o
+add wave -noupdate -group top /main/DUT/pps_o
+add wave -noupdate -group top /main/DUT/dac_helper_load_o
+add wave -noupdate -group top /main/DUT/dac_helper_value_o
+add wave -noupdate -group top /main/DUT/dac_main_load_o
+add wave -noupdate -group top /main/DUT/dac_main_value_o
+add wave -noupdate -group top /main/DUT/pll_status_i
+add wave -noupdate -group top /main/DUT/pll_mosi_o
+add wave -noupdate -group top /main/DUT/pll_miso_i
+add wave -noupdate -group top /main/DUT/pll_sck_o
+add wave -noupdate -group top /main/DUT/pll_cs_n_o
+add wave -noupdate -group top /main/DUT/pll_sync_n_o
+add wave -noupdate -group top /main/DUT/pll_reset_n_o
+add wave -noupdate -group top /main/DUT/uart_txd_o
+add wave -noupdate -group top /main/DUT/uart_rxd_i
+add wave -noupdate -group top /main/DUT/ljd_dac_main_sync_n_o
+add wave -noupdate -group top /main/DUT/ljd_dac_main_sclk_o
+add wave -noupdate -group top /main/DUT/ljd_dac_main_data_o
+add wave -noupdate -group top /main/DUT/ljd_loopback_i
+add wave -noupdate -group top /main/DUT/ljd_loopback_o
+add wave -noupdate -group top /main/DUT/ljd_clk1_en
+add wave -noupdate -group top /main/DUT/ljd_clk2_en
+add wave -noupdate -group top /main/DUT/ljd_detected_o
+add wave -noupdate -group top /main/DUT/ljd_osc_freq_i
+add wave -noupdate -group top /main/DUT/ljd_pll_mosi_o
+add wave -noupdate -group top /main/DUT/ljd_pll_miso_i
+add wave -noupdate -group top /main/DUT/ljd_pll_sck_o
+add wave -noupdate -group top /main/DUT/ljd_pll_cs_n_o
+add wave -noupdate -group top /main/DUT/ljd_pll_sync_n_o
+add wave -noupdate -group top /main/DUT/ljd_pll_reset_n_o
+add wave -noupdate -group top /main/DUT/ljd_pll_locked_i
+add wave -noupdate -group top /main/DUT/clk_en_o
+add wave -noupdate -group top /main/DUT/clk_sel_o
+add wave -noupdate -group top /main/DUT/clk_dmtd_divsel_o
+add wave -noupdate -group top /main/DUT/uart_sel_o
+add wave -noupdate -group top /main/DUT/phys_o
+add wave -noupdate -group top /main/DUT/phys_i
+add wave -noupdate -group top /main/DUT/led_link_o
+add wave -noupdate -group top /main/DUT/led_act_o
+add wave -noupdate -group top /main/DUT/gpio_o
+add wave -noupdate -group top /main/DUT/gpio_i
+add wave -noupdate -group top /main/DUT/i2c_scl_oen_o
+add wave -noupdate -group top /main/DUT/i2c_scl_o
+add wave -noupdate -group top /main/DUT/i2c_scl_i
+add wave -noupdate -group top /main/DUT/i2c_sda_oen_o
+add wave -noupdate -group top /main/DUT/i2c_sda_o
+add wave -noupdate -group top /main/DUT/i2c_sda_i
+add wave -noupdate -group top /main/DUT/rts_si57x_scl_oen_o
+add wave -noupdate -group top /main/DUT/rts_si57x_sda_oen_o
+add wave -noupdate -group top /main/DUT/rts_si57x_scl_i
+add wave -noupdate -group top /main/DUT/rts_si57x_sda_i
+add wave -noupdate -group top /main/DUT/aux_scl_oen_o
+add wave -noupdate -group top /main/DUT/aux_sda_oen_o
+add wave -noupdate -group top /main/DUT/aux_scl_o
+add wave -noupdate -group top /main/DUT/aux_sda_o
+add wave -noupdate -group top /main/DUT/aux_scl_i
+add wave -noupdate -group top /main/DUT/aux_sda_i
+add wave -noupdate -group top /main/DUT/mb_fan1_pwm_o
+add wave -noupdate -group top /main/DUT/mb_fan2_pwm_o
+add wave -noupdate -group top /main/DUT/spll_dbg_o
+add wave -noupdate -group top /main/DUT/sel_clk_sys_o
+add wave -noupdate -group top /main/DUT/rts_gpio_o
+add wave -noupdate -group top /main/DUT/rts_gpio_i
+add wave -noupdate -group top /main/DUT/cnx_slave_in
+add wave -noupdate -group top /main/DUT/cnx_slave_out
+add wave -noupdate -group top /main/DUT/bridge_master_in
+add wave -noupdate -group top /main/DUT/bridge_master_out
+add wave -noupdate -group top /main/DUT/cnx_master_in
+add wave -noupdate -group top /main/DUT/cnx_master_out
+add wave -noupdate -group top /main/DUT/cnx_endpoint_in
+add wave -noupdate -group top /main/DUT/cnx_endpoint_out
+add wave -noupdate -group top /main/DUT/clk_rx_vec
+add wave -noupdate -group top /main/DUT/clk_rx_sampled_vec
+add wave -noupdate -group top /main/DUT/endpoint_src_out
+add wave -noupdate -group top /main/DUT/endpoint_src_in
+add wave -noupdate -group top /main/DUT/endpoint_snk_out
+add wave -noupdate -group top /main/DUT/endpoint_snk_in
+add wave -noupdate -group top /main/DUT/wrfreg_src_out
+add wave -noupdate -group top /main/DUT/wrfreg_src_in
+add wave -noupdate -group top /main/DUT/swc_src_out
+add wave -noupdate -group top /main/DUT/swc_src_in
+add wave -noupdate -group top /main/DUT/swc_snk_out
+add wave -noupdate -group top /main/DUT/swc_snk_in
+add wave -noupdate -group top /main/DUT/dummy_snk_in
+add wave -noupdate -group top /main/DUT/dummy_src_in
+add wave -noupdate -group top /main/DUT/dummy_src_out
+add wave -noupdate -group top /main/DUT/rtu_req
+add wave -noupdate -group top /main/DUT/rtu_rsp
+add wave -noupdate -group top /main/DUT/rtu_req_ack
+add wave -noupdate -group top /main/DUT/rtu_full
+add wave -noupdate -group top /main/DUT/rtu_rsp_ack
+add wave -noupdate -group top /main/DUT/rtu_rq_abort
+add wave -noupdate -group top /main/DUT/rtu_rsp_abort
+add wave -noupdate -group top /main/DUT/swc_rtu_ack
+add wave -noupdate -group top /main/DUT/sel_clk_sys
+add wave -noupdate -group top /main/DUT/sel_clk_sys_int
+add wave -noupdate -group top /main/DUT/switchover_cnt
+add wave -noupdate -group top /main/DUT/rst_n_sys
+add wave -noupdate -group top /main/DUT/pps_p_main
+add wave -noupdate -group top /main/DUT/txtsu_timestamps_ack
+add wave -noupdate -group top /main/DUT/txtsu_timestamps
+add wave -noupdate -group top /main/DUT/tru_enabled
+add wave -noupdate -group top /main/DUT/rtu_events
+add wave -noupdate -group top /main/DUT/ep_events
+add wave -noupdate -group top /main/DUT/nic_events
+add wave -noupdate -group top /main/DUT/rmon_events
+add wave -noupdate -group top /main/DUT/dummy_events
+add wave -noupdate -group top /main/DUT/rst_periph_ref_n
+add wave -noupdate -group top /main/DUT/rst_periph_dmtd_n
+add wave -noupdate -group top /main/DUT/rst_periph_rxclk_n
+add wave -noupdate -group top /main/DUT/rst_periph_txclk_n
+add wave -noupdate -group top /main/DUT/rst_ref_n
+add wave -noupdate -group top /main/DUT/rst_ext_n
+add wave -noupdate -group top /main/DUT/rst_dmtd_n
+add wave -noupdate -group top /main/DUT/vic_irqs
+add wave -noupdate -group top /main/DUT/txtsu_irq
+add wave -noupdate -group top /main/DUT/nic_irq
+add wave -noupdate -group top /main/DUT/rtu_irq
+add wave -noupdate -group top /main/DUT/pstats_irq
+add wave -noupdate -group top /main/DUT/control0
+add wave -noupdate -group top /main/DUT/trig0
+add wave -noupdate -group top /main/DUT/trig1
+add wave -noupdate -group top /main/DUT/trig2
+add wave -noupdate -group top /main/DUT/trig3
+add wave -noupdate -group top /main/DUT/t0
+add wave -noupdate -group top /main/DUT/t1
+add wave -noupdate -group top /main/DUT/t2
+add wave -noupdate -group top /main/DUT/t3
+add wave -noupdate -group top /main/DUT/rst_n_periph
+add wave -noupdate -group top /main/DUT/link_kill
+add wave -noupdate -group top /main/DUT/rst_n_swc
+add wave -noupdate -group top /main/DUT/swc_nomem
+add wave -noupdate -group top /main/DUT/swc_wdog_out
+add wave -noupdate -group top /main/DUT/ep_stop_traffic
+add wave -noupdate -group top /main/DUT/ep_links_up
+add wave -noupdate -group top /main/DUT/cpu_irq_n
+add wave -noupdate -group top /main/DUT/pps_csync
+add wave -noupdate -group top /main/DUT/pps_valid
+add wave -noupdate -group top /main/DUT/gpio_out
+add wave -noupdate -group top /main/DUT/gpio_in
+add wave -noupdate -group top /main/DUT/dummy
+add wave -noupdate -group top /main/DUT/tru_req
+add wave -noupdate -group top /main/DUT/tru_resp
+add wave -noupdate -group top /main/DUT/rtu2tru
+add wave -noupdate -group top /main/DUT/ep2tru
+add wave -noupdate -group top /main/DUT/tru2ep
+add wave -noupdate -group top /main/DUT/swc2tru_req
+add wave -noupdate -group top /main/DUT/tm_utc
+add wave -noupdate -group top /main/DUT/tm_cycles
+add wave -noupdate -group top /main/DUT/tm_time_valid
+add wave -noupdate -group top /main/DUT/pps_o_predelay
+add wave -noupdate -group top /main/DUT/ppsdel_tap_out
+add wave -noupdate -group top /main/DUT/ppsdel_tap_in
+add wave -noupdate -group top /main/DUT/ppsdel_tap_wr_in
+add wave -noupdate -group top /main/DUT/shaper_request
+add wave -noupdate -group top /main/DUT/shaper_drop_at_hp_ena
+add wave -noupdate -group top /main/DUT/fc_rx_pause
+add wave -noupdate -group top /main/DUT/global_pause
+add wave -noupdate -group top /main/DUT/dbg_n_regs
+add wave -noupdate -group top /main/DUT/ep_dbg_data_array
+add wave -noupdate -group top /main/DUT/ep_dbg_k_array
+add wave -noupdate -group top /main/DUT/ep_dbg_rx_buf_array
+add wave -noupdate -group top /main/DUT/ep_dbg_fab_pipes_array
+add wave -noupdate -group top /main/DUT/ep_dbg_tx_pcs_wr_array
+add wave -noupdate -group top /main/DUT/ep_dbg_tx_pcs_rd_array
+add wave -noupdate -group top /main/DUT/dbg_chps_id
+add wave -noupdate -group top /main/DUT/nic_rtu_rsp
+add wave -noupdate -group top /main/DUT/nic_rtu_ack
+add wave -noupdate -group top /main/DUT/ljd_detected
+add wave -noupdate -group xbar /main/DUT/U_Intercon/clk_sys_i
+add wave -noupdate -group xbar /main/DUT/U_Intercon/rst_n_i
+add wave -noupdate -group xbar /main/DUT/U_Intercon/slave_i
+add wave -noupdate -group xbar /main/DUT/U_Intercon/slave_o
+add wave -noupdate -group xbar /main/DUT/U_Intercon/msi_master_i
+add wave -noupdate -group xbar /main/DUT/U_Intercon/msi_master_o
+add wave -noupdate -group xbar /main/DUT/U_Intercon/master_i
+add wave -noupdate -group xbar -expand /main/DUT/U_Intercon/master_o
+add wave -noupdate -group xbar /main/DUT/U_Intercon/msi_slave_i
+add wave -noupdate -group xbar /main/DUT/U_Intercon/msi_slave_o
+add wave -noupdate -group xbar /main/DUT/U_Intercon/master_i_1
+add wave -noupdate -group xbar /main/DUT/U_Intercon/master_o_1
+add wave -noupdate -group xbar /main/DUT/U_Intercon/sdb_sel
+add wave -noupdate -group xbar /main/DUT/U_Intercon/c_layout
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/clk_sys_i
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/rst_n_i
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/irq_i
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/dwb_o
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/dwb_i
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/host_slave_i
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/host_slave_o
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/cpu_rst
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/cpu_rst_d
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/im_addr
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/im_data
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/im_valid
+add wave -noupdate -group cpu /main/DUT/U_RT_Subsystem/U_CPU/ha_im_addr
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