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White Rabbit Switch - Gateware
Commit f0137c5c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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rudimentary testbench for the RISC-V RT subsys

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testbench/wrsw_rt_subsystem/bus_device.svh 0 → 100644
View file @ f0137c5c
//------------------------------------------------------------------------------
// CERN BE-CEM-EDL
// General Cores Library
// https://www.ohwr.org/projects/general-cores
//------------------------------------------------------------------------------
//
// units: gencores_sim_pkg
//
// description: Shared classes and interfaces for the gencores SV simulations
//
//------------------------------------------------------------------------------
// Copyright CERN 2010-2019
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`include "simdrv_defs.svh"
class CBusDevice;
protected CBusAccessor m_acc;
protected uint64_t m_base;
function new(CBusAccessor acc, uint64_t base);
m_acc = acc;
m_base = base;
endfunction // new
virtual task automatic writel(uint32_t addr, uint32_t val);
m_acc.write(m_base + addr, val);
endtask // writel
virtual task automatic readl(uint32_t addr, output uint32_t val);
automatic uint64_t val64;
m_acc.read(m_base + addr, val64);
val = val64;
endtask // readl
virtual task automatic set_bits(uint32_t addr, uint32_t bits);
uint32_t r;
readl(addr, r);
r |= bits;
writel(addr, r);
endtask
virtual task automatic clear_bits(uint32_t addr, uint32_t bits);
uint32_t r;
readl(addr, r);
r &= ~bits;
writel(addr, r);
endtask
endclass // CBusDevice
testbench/wrsw_rt_subsystem/main.sv 0 → 100644
View file @ f0137c5c
`timescale 1ns/1ps
`include "simdrv_defs.svh"
`include "vhd_wishbone_master.svh"
`include "bus_device.svh"
`define WRS_BASE_RT_SUBSYSTEM 'h00000000
`define WRS_RT_BASE_MAILBOX 'h00000000
`define WRS_RT_BASE_URV_BOOT 'h00010900
`define WRC_CPU_CSR_REG_RESET 'h00000000
`define WRC_CPU_CSR_REG_UADDR 'h00000004
`define WRC_CPU_CSR_REG_UDATA 'h00000008
class RISCVLoader extends CBusDevice;
function new(CBusAccessor acc, uint64_t base);
super.new(acc, base);
endfunction
task automatic load_binary( string filename );
int f = $fopen(filename,"rb");
int rv;
uint32_t uaddr = 0;
time t_start = $time;
$display("Loading %s", filename);
writel( `WRC_CPU_CSR_REG_RESET, 1 );
while( !$feof(f) )
begin
uint32_t udata;
rv = $fread(udata, f);
if (rv != 4 )
break;
writel( `WRC_CPU_CSR_REG_UADDR, uaddr );
writel( `WRC_CPU_CSR_REG_UDATA, udata );
uaddr++;
end
writel( `WRC_CPU_CSR_REG_RESET, 0 );
$display("CPU boot took %.0f us", real'($time - t_start) / real'(1us));
$fclose(f);
endtask
endclass
module main;
reg clk_sys = 0;
reg rst_sys_n = 0;
IVHDWishboneMaster
inst_sys_bus_master (
.clk_i(clk_sys),
.rst_n_i(rst_sys_n)
);
always #8ns clk_sys <= ~clk_sys;
initial begin
repeat(3) @(posedge clk_sys) ;
rst_sys_n <= 1;
end
scb_top_bare
#(
.g_simulation(1'b1)
) DUT (
.sys_rst_n_i(rst_sys_n),
//System clock 62.5 MHz
.clk_sys_i(clk_sys),
//62.5 MHz timing reference (from the AD9516 PLL output QDRII_CLK)
.clk_ref_i(clk_sys),
//62.5+ MHz DMTD offset clock (from the CDCM62001 PLL output DMTDCLK_MAIN)
.clk_dmtd_i(clk_sys),
//Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
//for re-phasing the 10 MHz input as well as clocking the
.clk_aux_i(1'b0),
.clk_ext_mul_i (2'b00),
.clk_ext_mul_locked_i(1'b0),
.clk_aux_p_o (),
.clk_aux_n_o (),
.clk_500_o (),
//Master wishbone bus (from the CPU bridge)
.cpu_wb_i ( inst_sys_bus_master.out ),
.cpu_wb_o ( inst_sys_bus_master.in ),
.cpu_irq_n_o(),
//Timing I/O
.pps_i (1'b0),
.ppsin_term_o(),
.pps_o (),
//DAC Drive
.dac_helper_load_o(),
.dac_helper_value_o(),
.dac_main_load_o(),
.dac_main_value_o(),
//AD9516 PLL Control signals
.pll_status_i (1'b0),
.pll_mosi_o (),
.pll_miso_i (1'b0),
.pll_sck_o (),
.pll_cs_n_o (),
.pll_sync_n_o (),
.pll_reset_n_o(),
.uart_txd_o(),
.uart_rxd_i(1'b1),
//Low Jitter Daughterboard support
.ljd_dac_main_sync_n_o(),
.ljd_dac_main_sclk_o (),
.ljd_dac_main_data_o (),
//Misc pins
//GTX clock fanout enable
.clk_en_o(),
//GTX clock fanout source select
.clk_sel_o(),
//DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
.clk_dmtd_divsel_o(),
//UART source selection (FPGA/DBGU)
.uart_sel_o()
);
initial begin
CBusAccessor acc;
RISCVLoader loader;
uint64_t rv;
#1us;
acc = inst_sys_bus_master.get_accessor();
loader = new( acc, `WRS_BASE_RT_SUBSYSTEM + `WRS_RT_BASE_URV_BOOT );
$display("Loading...\n");
loader.load_binary("rt_cpu_v4.bin");
#100us; // give the CPU a while
acc.read( `WRS_BASE_RT_SUBSYSTEM + `WRS_RT_BASE_MAILBOX, rv );
$display("MBOX signature: %x", rv );
$stop;
end
endmodule
testbench/wrsw_rt_subsystem/run.do 0 → 100644
View file @ f0137c5c
vsim -L unisim -t 1ps work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 600us
wave zoomfull
radix -hexadecimal
testbench/wrsw_rt_subsystem/wave.do 0 → 100644
View file @ f0137c5c
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