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White Rabbit Switch - Gateware
Commit f11df4c5 authored by Adam Wujek's avatar Adam Wujek
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.gitlab-ci.yml: test3 

Signed-off-by: 's avatarAdam Wujek <dev_public@wujek.eu>
parent a07e4d71
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      .gitlab-ci.yml
      View file @ f11df4c5
      ......@@ -32,10 +32,13 @@ job_scb_top_sim:
      job_scb_top_8p_syn:
      stage: syn
      tags:
      - xilinx_ISE_14.7
      - xilinx_ISE_14.7
      image: gitlab-registry.cern.ch/be-cem-edl/evergreen/gitlab-ci/xilinx-ise14.7
      before_script:
      - ls
      script:
      - /entrypoint.sh
      - source ~/setup_ise147.sh
      #- /entrypoint.sh
      #- source ~/setup_ise147.sh
      - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
      - echo ${CI_PROJECT_DIR}
      - cd ${CI_PROJECT_DIR}
      ......@@ -44,25 +47,28 @@ job_scb_top_8p_syn:
      - ls -l ..
      - du -sh *
      - cd top/bare_top
      - python gen_sdbsyn.py --project wr_switch
      - which python
      - python2.7 gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_18p --ver "14.7"
      - cat synthesis_descriptor.vhd
      - find / | grep hdlmake
      - cd ../../modules/wrsw_hwiu
      - python gen_ver.py
      - python2.7 gen_ver.py
      - cat gw_ver_pkg.vhd
      - cd ../../syn/scb_8ports
      - which hdlmake
      - hdlmake --version
      - hdlmake makefile
      - make
      - grep '^All constraints were met.$' *.par || echo "Not all constraints were met!" && false
      after_script:
      - du -sh *
      - tar cJvf ../repo.tar.xz --exclude=.git *
      - mv ../repo.tar.xz .
      - tar cJvf syn-report.tar.xz syn
      - tar cjvf ../repo.tar.bz2 --exclude=.git *
      - mv ../repo.tar.bz2 .
      - tar cjvf syn-report.tar.bz2 syn
      - ls -l .
      artifacts:
      when: always
      name: SCB_TOP_8P_CI_$CI_JOB_ID
      name: wr-switch-hdl_8P_CI_$CI_JOB_ID
      paths:
      - syn/scb_8ports/*.syr
      - syn/scb_8ports/*.mrp
      ......@@ -70,8 +76,8 @@ job_scb_top_8p_syn:
      - syn/scb_8ports/*.bin
      - syn/scb_8ports/*.par
      - syn/scb_8ports/*.twr
      - syn-report.tar.xz
      - repo.tar.xz
      - syn-report.tar.bz2
      - repo.tar.bz2
      job_scb_top_18p_syn:
      stage: syn
      ......@@ -83,8 +89,9 @@ job_scb_top_18p_syn:
      - source ~/setup_ise147.sh
      - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
      - cd top/bare_top
      - python gen_sdbsyn.py --project wr_switch
      - python2.7 gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_8p --ver "14.7"
      - cat synthesis_descriptor.vhd
      - find / | grep hdlmake
      - cd ../../modules/wrsw_hwiu
      - python gen_ver.py
      - cat gw_ver_pkg.vhd
      ......@@ -93,14 +100,15 @@ job_scb_top_18p_syn:
      - hdlmake --version
      - hdlmake makefile
      - make
      - grep '^All constraints were met.$' *.par || echo "Not all constraints were met!" && false
      after_script:
      - du -sh *
      - tar cJvf ../repo.tar.xz --exclude=.git *
      - mv ../repo.tar.xz .
      - tar cJvf syn-report.tar.xz syn
      - tar cjvf ../repo.tar.bz2 --exclude=.git *
      - mv ../repo.tar.bz2 .
      - tar cjvf syn-report.tar.bz2 syn
      - ls -l .
      artifacts:
      name: SCB_TOP_18P_CI_$CI_JOB_ID
      name: wr-switch-hdl_18P_CI_$CI_JOB_ID
      paths:
      - syn/scb_18ports/*.syr
      - syn/scb_18ports/*.mrp
      ......@@ -108,5 +116,5 @@ job_scb_top_18p_syn:
      - syn/scb_18ports/*.bin
      - syn/scb_18ports/*.par
      - syn/scb_18ports/*.twr
      - syn-report.tar.xz
      - repo.tar.xz
      - syn-report.tar.bz2
      - repo.tar.bz2
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