TRU: added simulation of a network of 3 WR switches (scb_to) - firt working…

TRU: added simulation of a network of 3 WR switches (scb_to) - firt working versionm needs further work

TRU: added simulation of a network of 3 WR switches (scb_to) - firt working…
TRU: added simulation of a network of 3 WR switches (scb_to) - firt working versionm needs further work
f67e4c9e · Maciej Lipinski · ee48b5c6 · f67e4c9e · f67e4c9e · f67e4c9e
Commit f67e4c9e authored Nov 09, 2012 by Maciej Lipinski
7 changed files
--- a/modules/wrsw_rtu/rtu_port_new.vhd
+++ b/modules/wrsw_rtu/rtu_port_new.vhd
@@ -522,16 +522,22 @@ begin
              if(mirror_port_src_rx = '1' or mirror_port_src_tx = '1') then
                -- if mirroring is enabled, and this port is source of mirror traffic, we don't drop
                -- the traffic, 
-                if(drop = '1') then
+                if(drop = '1' and mirror_port_src_rx = '1') then
                  -- forward only to the mirror (dst) port
                  -- (eliminate self-forward)
                  rsp.port_mask     <= f_set_bit(rtu_str_config_i.mirror_port_dst,'0',g_port_index) ;
+                  rsp.drop          <= '0';
                else
                  -- forward to "normal forwarding ports" + mirror (dst) port
                  -- (eliminate self-forward)
-                  rsp.port_mask     <= f_set_bit(forwarding_and_mirror_mask,'0',g_port_index); 
+                  rsp.drop          <= drop;
+                  if(drop = '1') then
+                    rsp.port_mask    <= (others=> '0');
+                  else
+                   rsp.port_mask     <= f_set_bit(forwarding_and_mirror_mask,'0',g_port_index); 
+                  end if;                    
                end if;
-                rsp.drop          <= '0';
              else
                -- normal forwarding
                -- (eliminate self-forward)

--- a/sim/simdrv_rtu.sv
+++ b/sim/simdrv_rtu.sv
@@ -53,8 +53,7 @@ class CRTUSimDriver;
   extern task set_bus(CBusAccessor _bus, int _base_addr);
   extern task add_hash_entry(rtu_filtering_entry_t ent);
-   extern task set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en);
+   extern task set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en, bit dbg = 0);
   extern task add_static_rule(bit[7:0] dmac[], bit[31:0] dpm);
   extern task add_vlan_entry(int vlan_id, rtu_vlan_entry_t ent);
   extern task poll_ufifo();
@@ -287,18 +286,18 @@ task CRTUSimDriver::add_hash_entry(rtu_filtering_entry_t ent);
 endtask // CRTUSimDriver
-task CRTUSimDriver::set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en);
+task CRTUSimDriver::set_port_config(int port, bit pass_all, bit pass_bpdu, bit learn_en, bit dbg = 0);
   uint64_t rv, tmp;
   bus.read(base_addr + `ADDR_RTU_PSR, rv);
-   $display("PSel: %d supported ports, configuration for port %d:", (rv>>8) & 'hff, port);
+   if(dbg) $display("PSel: %d supported ports, configuration for port %d:", (rv>>8) & 'hff, port);
-   if(learn_en  == 1) begin tmp = tmp | `RTU_PCR_LEARN_EN;  $display("learn"); end;
+   if(learn_en  == 1) begin tmp = tmp | `RTU_PCR_LEARN_EN; if(dbg)  $display("learn"); end;
-   if(pass_all  == 1) begin tmp = tmp | `RTU_PCR_PASS_ALL;  $display("pass all"); end;
+   if(pass_all  == 1) begin tmp = tmp | `RTU_PCR_PASS_ALL; if(dbg)  $display("pass all"); end;
-   if(pass_bpdu == 1) begin tmp = tmp | `RTU_PCR_PASS_BPDU; $display("pass bpdu"); end;
+   if(pass_bpdu == 1) begin tmp = tmp | `RTU_PCR_PASS_BPDU;if(dbg)  $display("pass bpdu"); end;
-   tmp = `RTU_PCR_B_UNREC | tmp; $display("broadcast unrecognized");
+   tmp = `RTU_PCR_B_UNREC | tmp; if(dbg) $display("broadcast unrecognized");
   bus.write(base_addr + `ADDR_RTU_PSR, port);
   bus.write(base_addr + `ADDR_RTU_PCR, tmp);

--- a/testbench/scb_network_top/Manifest.py
+++ b/testbench/scb_network_top/Manifest.py
+target = "xilinx"
+action = "simulation"
+syn_device = "XC6VLX130T"
+fetchto = "../../ip_cores"
+vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
+files = [ "main.sv" ]
+modules = { "local" : ["../../", "../../top/bare_top"] }
--- a/testbench/scb_network_top/main.sv
+++ b/testbench/scb_network_top/main.sv
--- a/testbench/scb_network_top/run.do
+++ b/testbench/scb_network_top/run.do
+make -f Makefile
+#vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
+vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+# do wave_new.do
+#do wave-master.do
+#do wave-allports.do
+radix -hexadecimal
+run 4000us
+wave zoomfull
+radix -hexadecimal
--- a/testbench/scb_network_top/scb_top_sim_svwrap.svh
+++ b/testbench/scb_network_top/scb_top_sim_svwrap.svh
--- a/testbench/scb_network_top/simdrv_wr_endpoint.svh
+++ b/testbench/scb_network_top/simdrv_wr_endpoint.svh
+`ifndef __SIMDRV_WR_ENDPOINT_SVH
+`define __SIMDRV_WR_ENDPOINT_SVH 1
+`timescale 1ns/1ps
+`include "simdrv_defs.svh"
+`include "endpoint_regs.v"
+class CSimDrv_WR_Endpoint;
+   protected CBusAccessor m_acc;
+   protected uint64_t m_base;
+   function new(CBusAccessor acc, uint64_t base);     
+      m_acc   = acc;
+      m_base  = base;
+   endfunction // new
+   task vlan_egress_untag(int vid, int untag);
+      m_acc.write(m_base + `ADDR_EP_VCR1, vid | ((untag ? 1: 0) << 12));
+   endtask // vlan_egress_untag
+   task pfilter_load_microcode(uint64_t mcode[]);
+      int i;
+      for(i=0;i<mcode.size();i++)
+        begin
+           m_acc.write(m_base + `ADDR_EP_PFCR1, (mcode[i] & 'hfff) << `EP_PFCR1_MM_DATA_LSB_OFFSET);
+           m_acc.write(m_base + `ADDR_EP_PFCR0, 
+                       (i << `EP_PFCR0_MM_ADDR_OFFSET) | 
+                       (((mcode[i] >> 12) & 'hffffff) << `EP_PFCR0_MM_DATA_MSB_OFFSET) |
+                       `EP_PFCR0_MM_WRITE);
+        end
+   endtask // pfilter_load_microcde
+   task pfilter_enable(int enable);
+      m_acc.write(m_base + `ADDR_EP_PFCR0, enable ? `EP_PFCR0_ENABLE: 0);
+   endtask // pfilter_enable
+`define EP_QMODE_VLAN_DISABLED 3
+   task init(int port_id);
+      m_acc.write(m_base + `ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN | (port_id << `EP_ECR_PORTID_OFFSET)) ;
+      m_acc.write(m_base + `ADDR_EP_RFCR, 1518 << `EP_RFCR_MRU_OFFSET);
+      m_acc.write(m_base + `ADDR_EP_VCR0, `EP_QMODE_VLAN_DISABLED << `EP_VCR0_QMODE_OFFSET);
+      m_acc.write(m_base + `ADDR_EP_TSCR, `EP_TSCR_EN_RXTS | `EP_TSCR_EN_TXTS);
+   endtask // init
+   task automatic mdio_read(int addr, output int val);
+      uint64_t rval;
+      m_acc.write(m_base + `ADDR_EP_MDIO_CR, (addr>>2) << 16, 4);
+      while(1)begin
+	 m_acc.read(m_base + `ADDR_EP_MDIO_ASR, rval, 4);
+	 if(rval & 'h80000000) begin
+	    val  = rval & 'hffff;
+	    return;
+	 end
+      end
+   endtask // mdio_read
+   task automatic mdio_write(int addr,int val);
+      uint64_t rval;
+      m_acc.write(m_base+`ADDR_EP_MDIO_CR, ((addr>>2) << 16) | `EP_MDIO_CR_RW | val);
+      while(1)begin
+	 #8ns;
+	 m_acc.read(m_base+`ADDR_EP_MDIO_ASR, rval);
+	 if(rval & 'h80000000)
+	   return;
+      end
+   endtask // automatic
+   task automatic check_link(ref int up);
+      reg[31:0] rval;
+      mdio_read(m_base + `ADDR_MDIO_MSR, rval);
+      up= (rval & `MDIO_MSR_LSTATUS) ? 1 : 0;
+   endtask // check_link
+endclass // CSimDrv_WR_Endpoint
+`endif //  `ifndef __SIMDRV_WR_ENDPOINT_SVH