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Commit fd450cee authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[generic-ing]: generic-azed hard-coded values (connected with rr_arbiter… 

swcore[generic-ing]: generic-azed hard-coded values (connected with rr_arbiter usage), identified limitation (in prio_encoder,TODO), added some description, tested with different port number values
parent 0054aa22
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Showing with 102 additions and 57 deletions
modules/wrsw_swcore/Manifest.py
View file @ fd450cee
......@@ -11,13 +11,10 @@ files = [
"swc_swcore_pkg.vhd",
"swc_block_alloc.vhd",
"swc_core.vhd",
#"swc_input_block.vhd",
#"swc_lost_pck_dealloc.vhd",
"swc_multiport_linked_list.vhd",
"swc_multiport_page_allocator.vhd",
"swc_multiport_pck_pg_free_module.vhd",
"swc_ob_prio_queue.vhd",
#"swc_output_block.vhd",
"swc_packet_mem.vhd",
"swc_packet_mem_read_pump.vhd",
"swc_packet_mem_write_pump.vhd",
......
modules/wrsw_swcore/swc_multiport_linked_list.vhd
View file @ fd450cee
......@@ -42,7 +42,8 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.CEIL;
use ieee.math_real.log2;
library work;
use work.swc_swcore_pkg.all;
......@@ -83,6 +84,8 @@ end swc_multiport_linked_list;
architecture syn of swc_multiport_linked_list is
constant c_arbiter_vec_width : integer := 2*g_num_ports;
constant c_arbiter_vec_width_log2 : integer := integer(CEIL(LOG2(real(2*g_num_ports-1))));
component generic_ssram_dualport_singleclock
generic (
......@@ -117,13 +120,13 @@ architecture syn of swc_multiport_linked_list is
signal ll_wr_data : std_logic_vector(g_page_addr_width -1 downto 0);
signal write_request_vec : std_logic_vector(g_num_ports*2-1 downto 0);
signal write_request_vec : std_logic_vector(c_arbiter_vec_width-1 downto 0);
signal read_request_vec : std_logic_vector(g_num_ports*2-1 downto 0);
signal read_request_vec : std_logic_vector(c_arbiter_vec_width-1 downto 0);
signal write_request_grant : std_logic_vector(4 downto 0);
signal write_request_grant : std_logic_vector(c_arbiter_vec_width_log2 - 1 downto 0);
signal read_request_grant : std_logic_vector(4 downto 0);
signal read_request_grant : std_logic_vector(c_arbiter_vec_width_log2 - 1 downto 0);
-- indicates that the granted request is valid
......@@ -216,8 +219,9 @@ begin -- syn
-- unnecessary delays
WRITE_ARB : swc_rr_arbiter
generic map (
g_num_ports => g_num_ports * 2,
g_num_ports_log2 => 5)
g_num_ports => c_arbiter_vec_width,
g_num_ports_log2 => c_arbiter_vec_width_log2 --5
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......@@ -228,8 +232,8 @@ begin -- syn
READ_ARB : swc_rr_arbiter
generic map (
g_num_ports => g_num_ports * 2,
g_num_ports_log2 => 5
g_num_ports => c_arbiter_vec_width,
g_num_ports_log2 => c_arbiter_vec_width_log2 -- 5
)
port map (
clk_i => clk_i,
......
modules/wrsw_swcore/swc_multiport_page_allocator.vhd
View file @ fd450cee
......@@ -44,6 +44,8 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.CEIL;
use ieee.math_real.log2;
library work;
use work.swc_swcore_pkg.all;
......@@ -84,6 +86,9 @@ end swc_multiport_page_allocator;
architecture syn of swc_multiport_page_allocator is
constant c_arbiter_vec_width : integer := 4*g_num_ports;
constant c_arbiter_vec_width_log2 : integer := integer(CEIL(LOG2(real(4*g_num_ports-1))));
signal pg_alloc : std_logic;
signal pg_free : std_logic;
signal pg_force_free : std_logic;
......@@ -106,14 +111,14 @@ architecture syn of swc_multiport_page_allocator is
-- the address of the bit :
-- * representing alloc request - is even [i*2]
-- * representing free request - is odd [i*2 + 1]
signal request_vec : std_logic_vector(g_num_ports*4-1 downto 0);
signal request_vec : std_logic_vector(c_arbiter_vec_width-1 downto 0);
-- address of the request which has been granted access
-- to page alloation core. the LSB bit indicates the kind of
-- operation:
-- * '0' - even address, so alloc operation
-- * '1' - odd address, so free operation
signal request_grant : std_logic_vector(5 downto 0);
signal request_grant : std_logic_vector(c_arbiter_vec_width_log2-1 downto 0);
-- used to indicate to the RR arbiter to start
-- processing next request,
......@@ -201,8 +206,8 @@ begin -- syn
-- unnecessary delays
ARB : swc_rr_arbiter
generic map (
g_num_ports => g_num_ports * 4,
g_num_ports_log2 => 6)
g_num_ports => c_arbiter_vec_width,
g_num_ports_log2 => c_arbiter_vec_width_log2)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......
modules/wrsw_swcore/swc_rr_arbiter.vhd
View file @ fd450cee
......@@ -42,6 +42,8 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
entity swc_rr_arbiter is
......@@ -64,18 +66,6 @@ end swc_rr_arbiter;
architecture syn of swc_rr_arbiter is
component swc_prio_encoder
generic (
g_num_inputs : integer range 2 to 64;
g_output_bits : integer range 1 to 6);
port (
in_i : in std_logic_vector(g_num_inputs-1 downto 0);
out_o : out std_logic_vector(g_output_bits-1 downto 0);
onehot_o : out std_logic_vector(g_num_inputs-1 downto 0);
mask_o : out std_logic_vector(g_num_inputs-1 downto 0);
zero_o : out std_logic);
end component;
signal request_mask : std_logic_vector(g_num_ports -1 downto 0);
signal request_mask_saved : std_logic_vector(g_num_ports -1 downto 0);
signal request_vec_masked : std_logic_vector(g_num_ports -1 downto 0);
......
testbench/swcore/Manifest.py
View file @ fd450cee
......@@ -3,17 +3,16 @@ action = "simulation"
#fetchto = "../../ip_cores"
#files = "swc_core.v4.sv"
files = [
# simulation for 7 ports (hard-coded)
"swc_core_wrapper_7ports.vhd",
"xswc_core_wrapper_7ports.svh",
"swc_core_7ports.sv",
# simulation for generic number of ports (set in swc_param_defs.svh for DUT and simulation)
"swc_core_wrapper_generic.svh",
"swc_core_generic.sv"
]
#vlog_opt="+incdir+../../../sim "
vlog_opt="+incdir+../../ip_cores/wr-cores/sim +incdir+../../ip_cores/wr-cores/sim/fabric_emu"
modules = {"local":
......
testbench/swcore/swc_core_generic.sv
View file @ fd450cee
// Fabric emulator example, showing 2 fabric emulators connected together and exchanging packets.
/*-------------------------------------------------------------------------------
-- Title : Switch Core Generic Testbench
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_core_generic.sv
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2012-02-07
-- Last update: 2012-02-07
-- Platform : FPGA-generic
-- Standard :
-------------------------------------------------------------------------------
-- Description: This is a testbench for SWcore, it is generic port_number-wise
-- It adapts to the port number set in the swc_param_defs.svh file.
-- Use DBG_ALLOC to turn off/on debugging of the page allocator (useful when you
-- start loosing pages)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-02-07 1.0 mlipinsk Created
------------------------------------------------------------------------------*/
`define c_clock_period 8
`define c_n_pcks_to_send 10
......@@ -284,7 +326,7 @@ module main_generic;
src[4] = new(U_wrf_source[4].get_accessor());
src[5] = new(U_wrf_source[5].get_accessor());
src[6] = new(U_wrf_source[6].get_accessor());
/*
src[7] = new(U_wrf_source[7].get_accessor());
src[8] = new(U_wrf_source[8].get_accessor());
src[9] = new(U_wrf_source[9].get_accessor());
......@@ -294,7 +336,7 @@ module main_generic;
src[13] = new(U_wrf_source[13].get_accessor());
src[14] = new(U_wrf_source[14].get_accessor());
src[15] = new(U_wrf_source[15].get_accessor());
src[16] = new(U_wrf_source[16].get_accessor());
/* src[16] = new(U_wrf_source[16].get_accessor());
src[17] = new(U_wrf_source[17].get_accessor());
*/
......@@ -305,7 +347,7 @@ module main_generic;
sink[4] = new(U_wrf_sink[4].get_accessor());
sink[5] = new(U_wrf_sink[5].get_accessor());
sink[6] = new(U_wrf_sink[6].get_accessor());
/*
sink[7] = new(U_wrf_sink[7].get_accessor());
sink[8] = new(U_wrf_sink[8].get_accessor());
sink[9] = new(U_wrf_sink[9].get_accessor());
......@@ -315,7 +357,7 @@ module main_generic;
sink[13] = new(U_wrf_sink[13].get_accessor());
sink[14] = new(U_wrf_sink[14].get_accessor());
sink[15] = new(U_wrf_sink[15].get_accessor());
sink[16] = new(U_wrf_sink[16].get_accessor());
/* sink[16] = new(U_wrf_sink[16].get_accessor());
sink[17] = new(U_wrf_sink[17].get_accessor());
*/
......@@ -341,7 +383,7 @@ module main_generic;
EthPacketGenerator gen;
int i;
int n_ports = `c_num_ports;
bit [`c_num_ports:0] mask;
// initialization
initPckSrcAndSink(src, sink, n_ports);
gen = new;
......@@ -354,8 +396,9 @@ module main_generic;
send_random_packet(src,txed, 0 /*port*/, 0 /*drop*/,7 /*prio*/, 2 /*mask*/);
for(i=0; i<10; i++) begin
send_random_packet(src,txed, i%7, 0,7 , 7);
for(i=0; i<(2*`c_num_ports - 1); i++) begin
mask = mask^(1<<(i%(`c_num_ports)));
send_random_packet(src,txed, i%(`c_num_ports), 0,7 , mask);
wait_cycles(500);
end
......@@ -491,23 +534,6 @@ module main_generic;
s = "";
for(j=0;j<`c_num_ports;j++) s = {s, $psprintf("%2d:%2d|",alloc_table[i].usecnt[j],alloc_table[i].port[j])};
$display("Page %4d: alloc = %4d [%s]",i,alloc_table[i].cnt,s);
//$display("Page %4d: alloc = %4d [%2d:%2d|%2d:%2d|%2d:%2d|%2d:%2d|%2d:%2d|%2d:%2d]<=|=>dealloc = %4d [%2d:%11b|%2d:%11b|%2d:%11b|%2d:%11b|%2d:%11b|%2d:%11b] ",
// i,
// alloc_table[i].cnt,
// alloc_table[i].usecnt[0], alloc_table[i].port[0],
// alloc_table[i].usecnt[1], alloc_table[i].port[1],
// alloc_table[i].usecnt[2], alloc_table[i].port[2],
// alloc_table[i].usecnt[3], alloc_table[i].port[3],
// alloc_table[i].usecnt[4], alloc_table[i].port[4],
// alloc_table[i].usecnt[5], alloc_table[i].port[5],
// dealloc_table[i].cnt,
// dealloc_table[i].usecnt[0], dealloc_table[i].port[0],
// dealloc_table[i].usecnt[1], dealloc_table[i].port[1],
// dealloc_table[i].usecnt[2], dealloc_table[i].port[2],
// dealloc_table[i].usecnt[3], dealloc_table[i].port[3],
// dealloc_table[i].usecnt[4], dealloc_table[i].port[4],
// dealloc_table[i].usecnt[5], dealloc_table[i].port[5]);
cnt++;
end
......
testbench/swcore/swc_param_defs.svh
View file @ fd450cee
`ifndef __SWC_PARAM_DEFS_SV
`define __SWC_PARAM_DEFS_SV
/******************** port number ******************************
* here you can define the number of ports of the swcore.
* It affects both: testbench and DUT !
* It means that the DUT will be configured to the set number of
* ports and testbench will be adapted to handle this number of
* ports
*
* REMARKS:
* 1) Currently, the testbench implementation is not fully generic
* (this is on the TODO list). this means that you need to
* modify appropriately :
* function initPckSrcAndSink() in swc_core_generic.sv
*
* 2) The max possible number of ports (which works) is 16, this
* is caused by the limitation of the *swc_prio_encoder*.
* This bug can be easily fixed, but the swcore will be deeply
* re-done very soon, so there is no use to do it before.
*
*/
////////////////////////////////////////////////////////////////
`define c_num_ports 16 //MAX: 16 //
////////////////////////////////////////////////////////////////
`define c_mem_size 65536 //c_swc_packet_mem_size,
`define c_page_size 64 //c_swc_page_size,
`define c_prio_num 8 // c_swc_output_prio_num,
`define c_max_pck_size 10 * 1024 // 10kB -- c_swc_max_pck_size,
`define c_num_ports 7 //c_swc_num_ports,
`define c_data_width 16 //c_swc_data_width,
`define c_ctrl_width 4 //c_swc_ctrl_width,
`define c_pck_pg_free_fifo_size ((65536/64)/2) //c_swc_freeing_fifo_size,
......
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