-
Grzegorz Daniluk authored
Fix for the issue 1063. In short, we need to keep in reset clock alignment fifo in the endpoint (native Virtex-6 FIFO) until GTX is locked and produces rx clock. That's what Xilinx document _ug363_ says. Otherwise, if this FIFO is not reset correctly I get strange behavior like asserting empty_o and almost_full_o in the same time.
22e38c23
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
general-cores @ 12c045eb | ||
wr-cores @ 77d23a1b | ||
.gitignore |