POWERING | Comments | Done | |
---|---|---|---|
1 | Redesign P085, IC32, to be at least 30A | Use WREN-like powering | |
2 | No need for ferrite beads on the DC/DC outputs; maybe leave for initial debugging | Relevant comment from previous review: Add a small ferrite in the +12V0 line to VDD (A7, A8) See also ZL9010M datasheet Figure 19 | |
3 | A lot of missing power vias near decoupling capacitors | ||
4 | Use standard coils: L74, L76, L75, L77 CMC windings are connected in parallel. That won't work. CMCs are very fragile to current imbalance. To make them work, use common ferrite core or multi-windong CMCs | ||
5 | Use VCCINT below FPGA as the DC/DC feedback | ||
6 | Design checklist XTP427 | ||
7 | SI and PI |
TO CHECK | Comments | Done | |
---|---|---|---|
1 | TR2: check input stage, assume GM clock as input | Relevant comment from previous review: Sheet 3: “GM_CLOCKING.SchDoc” and #44 (closed) | |
2 | IC49 LTC4358: what's the purpose? Check also D22 rating | Relevant comment from previous review: Consider to connect VDD pin of LTC4358 via a 100 ohm resistor a 100nF capacitor (“VDD Hold-Up Circuit” see figure 2b of LTC4358 datasheet) |
SCHEMATICS | Comments | Done | |
---|---|---|---|
1 | Add series 4k7 protection resistor in series with FANx_PRESENT input | Protect FPGA when somebody inserts fan with different wiring | |
2 | Connect D26 pin 5 to 3V3 and add series PWM input resistors | Protect fan controller when somebody inserts fan with different wiring | |
3 | Power sequencing graph: embed in sch as graphical object | ||
4 | PS_MIOS: check how's Linux driver support for I2C mux (IC20). Maybe for some of the stuff that needs to be frequently accessed (e.g. OLED?) would make sense to connect to PL and use PL-instantiated IIC ipcore | ||
5 | USB_interfaces: with proper EEPROM configuration, you can use FTDI chip not only for UART, but also as JTAG for the FPGA | Greg to provide DI/OT fw | |
6 | ESD7016MUTAG: leave the footprint | Check if pin 11, remote sense should be connected (ATX standard/PSU - remote sense on pin 11, useful if we do not have enough copper on power planes) | |
7 | TVS for FMC status lines instead of PESD3V3L1BA | Relevant comments from previous review: ESD protection on J15 signals? They are directly connected to the FPGA pins. Max voltage on pin is: HP VCCO =1V8 + 0.3 See Table 7; not sure how to interpret overshoot? For example ESD122DMYR might not be sufficient. And #44 (closed) | |
8 | USBC requires 5k1 pulldown resistors on CC lines to work as USB device | ||
9 | SFP I2C interface is not protected with TVS while the MGT IFC is | ||
10 | Connect D5, D6 pin 5 to 3V3 | It would lower the clamping voltage |
LAYOUT | Comments | Done | |
---|---|---|---|
1 | Have thermal on all SMD pads | No thermal bridges for SMD pads on top layer. This makes soldering challenging | |
2 | Acute copper on top layer and other layers | It will affect reliability | |
3 | DDR4_DQS8_x routed over split polygon | ||
4 | Tracks for decoupling capacitors are often too small | Set the track width equal to the diameter of the vias | |
5 | Floating Cu, unconnected trace around clocking | Should be connected to vias, leave for debugging | |
6 | In L2 there is thick (2mm) P3V8 trace that connects to other layers through very tiny vias (0.3mm hole size). Increase vias dimension. [X:165mm, Y: 150mm] | ||
7 | PMUbus: missing connectivity to the Power Supply | Data, Clock, Control, SMBALERT signals |
CONNECTORS | Comments | Done | |
---|---|---|---|
1 | J11/J13: replace edge fan connectors | PCB too thick | |
2 | J4: the USB3.1 connector needs to extend beyond PCB by min 0.5cm | Probably need a new connector. Currently the connector is hidden behind the front panel and cannot be used (see pic ) | |
3 | J10: consider using angled connector | With the cables, it barely fits in the enclosure, some danger to strain the cables | |
4 | J12: Move PSU-present/alarm connector closer to the front |
FINAL TOUCHES | Comments | Done | |
---|---|---|---|
1 | Is it allowed to put via in pads for decoupling capacitors located under the fpga? | ||
2 | Some designators are rotated | ||
3 | Enable PN view of ICs, like ESD7016MUTAG | ||
4 | Add annotation about power level at P5 input (it is 10MHz input) | ||
5 | Add teardrops | ||
6 | Missing licensing and URL in the silkscreen; WR logo of bad quality | ||
7 | Some traces are not routed, e.g. SATA_RX_P/N or SD_CTRL.SD_D0/2 | ||
8 | Check voltage rail nomenclature, ex. P3AV3 looks weird | ||
9 | Accute angles | ||
10 | The heatsink used seems to be too small | ||
11 | SMA connectors P6, P4, P5, P2, P3: make the order of the I/Os different (similar to what we have in the current WRS and divided into INs and OUTs), i.e., from left: PPS_OUT, 10MHz_OUT, AUX_ABSCAL, 10MHz_IN, PPS_IN | ||
12 | J8: "M.2 PCIe" -> if we decide to keep M.2 over SATA, replace "PCIe" with "SATA" |
---> Tom to implement main points
---> William on the final touches and checks
---> Book with Raphael the assembly of 3 prototypes on-site beginning of July!