Commit 47c1416b authored by jgabriel's avatar jgabriel

Fixed bugs detected in previous version of PCB. Added some modifications.

For more information see "SCB_Bugs_Changes.odt" file.
parent d0bdb6bc
......@@ -2,7 +2,7 @@ CPU_JTAG=JNTRST,JTDI,JTMS,JTCK,JRTCK,JTDO,JNRST
CPU_SSC=TF1,TK1,TD1,RD1,RK1,RF1
CPU_USB=USB_HDP_N,USB_HDP_P,USB_DDP_N,USB_DDP_P
ETH_100MHz=LED_ACT,LED_LINK,RX_N,RX_P,TX_N,TX_P,SHIELD
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDO,FPGA_TDI
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
......
DAC_CONTROL=DAC_DMTD_DIN,DAC_DMTD_SYNC,DAC_DMTD_SCLK,DAC_REF_DIN,DAC_REF_SYNC,DAC_REF_SCLK
PLL_CONTROL=CLK1_SEL,PLL_CS,PLL_STAT,PLL_LOCK,PLL_RESET,PLL_REFSEL,PLL_SCLK,PLL_SDO,PLL_SDI,PLL_SYNC
PLL_CONTROL=CLK_EN,CLK1_SEL,PLL_CS,PLL_STAT,PLL_LOCK,PLL_RESET,PLL_REFSEL,PLL_SCLK,PLL_SDO,PLL_SDI,PLL_SYNC
Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS,CLK1_SEL
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS,CLK1_SEL,CLK_EN
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N,MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N
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