Commit 0605e5d2 authored by Alessandro Rubini's avatar Alessandro Rubini

kernel modules: support up to 18 endpoints

parent ad7ed061
......@@ -149,8 +149,8 @@ static int __devinit wrn_probe(struct platform_device *pdev)
/* The ep structure is filled before calling ep_probe */
ep = netdev_priv(netdev);
ep->wrn = wrn;
ep->ep_regs = wrn->bases[WRN_FB_EP]; /* FIXME: works for 1EP */
//printk("ep %p, regs %i = %p\n", ep, i, ep->ep_regs);
ep->ep_regs = wrn->bases[WRN_FB_EP] + i * FPGA_SIZE_EACH_EP;
printk("ep %p, regs %i = %p\n", ep, i, ep->ep_regs);
ep->ep_number = i;
#if 0 /* FIXME: UPlink or not? */
if (i < WRN_NR_UPLINK)
......
......@@ -58,10 +58,10 @@ int wrn_calib_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
if (copy_from_user(&cal_req, rq->ifr_data, sizeof(cal_req)))
return -EFAULT;
#if 0
if (!(ep->ep_flags & BIT(WRN_EP_UP)))
return -EIO; /* was -EFAULT in minic */
#endif
if (0) { /* FIXME: what' coming out of this thing? */
if (!(ep->ep_flags & BIT(WRN_EP_UP)))
return -EIO; /* was -EFAULT in minic */
}
switch(cal_req.cmd) {
case WRN_CAL_TX_ON:
......
......@@ -47,6 +47,7 @@
#define FPGA_SIZE_NIC 0x00010000
#define FPGA_BASE_EP 0x10030000
#define FPGA_SIZE_EP 0x00010000
#define FPGA_SIZE_EACH_EP 0x200
#define FPGA_BASE_VIC 0x10050000
#define FPGA_SIZE_VIC 0x00001000
#define FPGA_BASE_TS 0x10051000
......@@ -57,17 +58,14 @@
enum fpga_blocks {
WRN_FB_NIC,
WRN_FB_EP,
WRN_FB_VIC, /* not mapped here (but in vic.ko) */
WRN_FB_VIC, /* not mapped here (but in wr-vic.ko) */
WRN_FB_TS,
WRN_FB_PPSG,
WRN_NR_OF_BLOCKS,
};
/* In addition to the above enumeration, mark out endpoints (FIXME: 1 only) */
#define WRN_NR_ENDPOINTS 1
#define WRN_FIRST_EP WRN_BLOCK_EP_UP0
#define WRN_LAST_EP WRN_FIRST_EP
//#define WRN_NR_UPLINK (WRN_BLOCK_EP_DP0 - WRN_BLOCK_EP_UP0)
/* In addition to the above enumeration, we scan for those many endpoints */
#define WRN_NR_ENDPOINTS 18
/* 8 tx and 8 rx descriptors */
#define WRN_NR_DESC 8
......
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