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White Rabbit Switch - Software
Commit 21076329 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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userspace: replaced redundant WB registers headers with the kernel ones

parent f45ee057
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userspace/Makefile
View file @ 21076329
...@@ -20,6 +20,7 @@ export ...@@ -20,6 +20,7 @@ export
# All targets must install as well, as later builds use headers/libs # All targets must install as well, as later builds use headers/libs
all: all:
ln -sf ../../kernel/wbgen-regs include/regs
for d in $(SUBDIRS); do $(MAKE) -C $$d $@ || exit 1; done for d in $(SUBDIRS); do $(MAKE) -C $$d $@ || exit 1; done
clean: clean:
......
userspace/include/hw/endpoint_mdio.h deleted 100644 → 0
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userspace/include/hw/endpoint_regs.h deleted 100644 → 0
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userspace/include/hw/pps_gen_regs.h deleted 100644 → 0
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/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Mon Apr 23 22:33:01 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#include <stdint.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Reset counter in reg: Control Register */
#define PPSG_CR_CNT_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable counter in reg: Control Register */
#define PPSG_CR_CNT_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Adjust offset in reg: Control Register */
#define PPSG_CR_CNT_ADJ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Set time in reg: Control Register */
#define PPSG_CR_CNT_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: PPS Pulse width in reg: Control Register */
#define PPSG_CR_PWIDTH_MASK WBGEN2_GEN_MASK(4, 28)
#define PPSG_CR_PWIDTH_SHIFT 4
#define PPSG_CR_PWIDTH_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define PPSG_CR_PWIDTH_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Nanosecond counter register */
/* definitions for register: SEC Counter register (least-significant part) */
/* definitions for register: SEC Counter register (most-significant part) */
/* definitions for register: Nanosecond adjustment register */
/* definitions for register: SEC Adjustment register (least-significant part) */
/* definitions for register: SEC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(SEC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
#define PPSG_REG_CNTR_NSEC 0x00000004
/* [0x8]: REG SEC Counter register (least-significant part) */
#define PPSG_REG_CNTR_SECLO 0x00000008
/* [0xc]: REG SEC Counter register (most-significant part) */
#define PPSG_REG_CNTR_SECHI 0x0000000c
/* [0x10]: REG Nanosecond adjustment register */
#define PPSG_REG_ADJ_NSEC 0x00000010
/* [0x14]: REG SEC Adjustment register (least-significant part) */
#define PPSG_REG_ADJ_SECLO 0x00000014
/* [0x18]: REG SEC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_SECHI 0x00000018
/* [0x1c]: REG External sync control register */
#define PPSG_REG_ESCR 0x0000001c
#endif
userspace/include/hw/rtu_regs.h deleted 100644 → 0
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userspace/libswitchhw/Makefile
View file @ 21076329
CC = $(CROSS_COMPILE)gcc CC = $(CROSS_COMPILE)gcc
AR = $(CROSS_COMPILE)ar AR = $(CROSS_COMPILE)ar
CFLAGS = -I. -O2 -I../include -DDEBUG -I./minilzo -g -I./lua-5.2.0/src/ CFLAGS = -I. -O2 -I../include -DDEBUG -g
OBJS = trace.o init.o fpga_io.o util.o pps_gen.o i2c.o pio_pins.o i2c_bitbang.o i2c_fpga_reg.o pio.o libshw_i2c.o i2c_sfp.o OBJS = trace.o init.o fpga_io.o util.o pps_gen.o i2c.o pio_pins.o i2c_bitbang.o i2c_fpga_reg.o pio.o libshw_i2c.o i2c_sfp.o
SCAN_OBJS = i2cscan.o SCAN_OBJS = i2cscan.o
......
userspace/libswitchhw/fpga_io.c
View file @ 21076329
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#include <switch_hw.h> #include <switch_hw.h>
#include <hw/fpga_regs.h> #include <fpga_io.h>
#define SMC_CS0_BASE 0x10000000 #define SMC_CS0_BASE 0x10000000
#define SMC_CS0_SIZE 0x200000 #define SMC_CS0_SIZE 0x200000
......
userspace/libswitchhw/i2c_fpga_reg.h
View file @ 21076329
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
#ifndef I2C_FPGA_REG_H #ifndef I2C_FPGA_REG_H
#define I2C_FPGA_REG_H #define I2C_FPGA_REG_H
#include <hw/fpga_regs.h> #include <fpga_io.h>
#include "i2c.h" #include "i2c.h"
#define FPGA_I2C_REG_PREL 0x00 #define FPGA_I2C_REG_PREL 0x00
......
userspace/libswitchhw/pps_gen.c
View file @ 21076329
/* PPS Generator driver */ /* PPS Generator driver */
/* Warning: references to "UTC" in the registers DO NOT MEAN actual UTC time, it's just a plain second counter
It doesn't care about leap seconds. */
#include <stdio.h> #include <stdio.h>
#include <string.h> #include <string.h>
#include <stddef.h>
#include <inttypes.h> #include <inttypes.h>
#include <sys/time.h> #include <sys/time.h>
#include <hw/fpga_regs.h> #include <fpga_io.h>
#include <hw/pps_gen_regs.h> #include <regs/ppsg-regs.h>
#include <switch_hw.h> #include <switch_hw.h>
#include <trace.h> #include <trace.h>
...@@ -14,6 +18,12 @@ ...@@ -14,6 +18,12 @@
/* Default width (in 8ns units) of the pulses on the PPS output */ /* Default width (in 8ns units) of the pulses on the PPS output */
#define PPS_WIDTH 100000 #define PPS_WIDTH 100000
#define ppsg_write(reg, val) \
_fpga_writel(FPGA_BASE_PPS_GEN + offsetof(struct PPSG_WB, reg), val)
#define ppsg_read(reg) \
_fpga_readl(FPGA_BASE_PPS_GEN + offsetof(struct PPSG_WB, reg))
int shw_pps_gen_init() int shw_pps_gen_init()
{ {
uint32_t cr; uint32_t cr;
...@@ -21,15 +31,15 @@ int shw_pps_gen_init() ...@@ -21,15 +31,15 @@ int shw_pps_gen_init()
cr = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_WIDTH); cr = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_WIDTH);
TRACE(TRACE_INFO, "Initializing PPS generator..."); TRACE(TRACE_INFO, "Initializing PPS generator...");
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, cr); ppsg_write(CR, cr);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECLO, 0); ppsg_write(ADJ_UTCLO, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECHI, 0); ppsg_write(ADJ_UTCHI, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, 0); ppsg_write(ADJ_NSEC, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, cr | PPSG_CR_CNT_SET); ppsg_write(CR, cr | PPSG_CR_CNT_SET);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, cr); ppsg_write(CR, cr);
_fpga_writel(FPGA_BASE_PPS_GEN + 0x1c, 0x6); /* enable PPS output */ ppsg_write(ESCR, 0x6); /* enable PPS output */
} }
/* Adjusts the nanosecond (refclk cycle) counter by atomically adding (how_much) cycles. */ /* Adjusts the nanosecond (refclk cycle) counter by atomically adding (how_much) cycles. */
...@@ -42,34 +52,34 @@ int shw_pps_gen_adjust(int counter, int64_t how_much) ...@@ -42,34 +52,34 @@ int shw_pps_gen_adjust(int counter, int64_t how_much)
if(counter == PPSG_ADJUST_NSEC) if(counter == PPSG_ADJUST_NSEC)
{ {
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECLO, 0); ppsg_write(ADJ_UTCLO, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECHI, 0); ppsg_write(ADJ_UTCHI, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, how_much); ppsg_write(ADJ_NSEC, how_much);
} else { } else {
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECLO, (uint32_t ) (how_much & 0xffffffffLL)); ppsg_write(ADJ_UTCLO, (uint32_t ) (how_much & 0xffffffffLL));
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECHI, (uint32_t ) (how_much >> 32) & 0xff); ppsg_write(ADJ_UTCHI, (uint32_t ) (how_much >> 32) & 0xff);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, 0); ppsg_write(ADJ_NSEC, 0);
} }
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CR) | PPSG_CR_CNT_ADJ); ppsg_write(CR, ppsg_read(CR) | PPSG_CR_CNT_ADJ);
return 0; return 0;
} }
/* Returns 1 when the adjustment operation is not yet finished */ /* Returns 1 when the adjustment operation is not yet finished */
int shw_pps_gen_busy() int shw_pps_gen_busy()
{ {
uint32_t cr = _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CR); uint32_t cr = ppsg_read(CR);
return cr& PPSG_CR_CNT_ADJ ? 0 : 1; return cr & PPSG_CR_CNT_ADJ ? 0 : 1;
} }
/* Enables/disables PPS output */ /* Enables/disables PPS output */
int shw_pps_gen_enable_output(int enable) int shw_pps_gen_enable_output(int enable)
{ {
uint32_t escr = _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR); uint32_t escr = ppsg_read(ESCR);
if(enable) if(enable)
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR, escr | PPSG_ESCR_PPS_VALID) ppsg_write(ESCR, escr | PPSG_ESCR_PPS_VALID)
else else
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR, escr & ~PPSG_ESCR_PPS_VALID); ppsg_write(ESCR, escr & ~PPSG_ESCR_PPS_VALID);
return 0; return 0;
} }
...@@ -80,9 +90,9 @@ void shw_pps_gen_read_time(uint64_t *seconds, uint32_t *nanoseconds) ...@@ -80,9 +90,9 @@ void shw_pps_gen_read_time(uint64_t *seconds, uint32_t *nanoseconds)
uint64_t sec1, sec2; uint64_t sec1, sec2;
do { do {
sec1 = (uint64_t)_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_SECLO) | (uint64_t)_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_SECHI) << 32; sec1 = (uint64_t)ppsg_read(CNTR_UTCLO) | (uint64_t)ppsg_read(CNTR_UTCHI) << 32;
ns_cnt = _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_NSEC); ns_cnt = ppsg_read(CNTR_NSEC);
sec2 = (uint64_t)_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_SECLO) | (uint64_t)_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_SECHI) << 32; sec2 = (uint64_t)ppsg_read(CNTR_UTCLO) | (uint64_t)ppsg_read(CNTR_UTCHI) << 32;
} while(sec2 != sec1); } while(sec2 != sec1);
if(seconds) *seconds = sec2; if(seconds) *seconds = sec2;
......
userspace/tools/Makefile
View file @ 21076329
...@@ -14,7 +14,6 @@ OBJDUMP = $(CROSS_COMPILE)objdump ...@@ -14,7 +14,6 @@ OBJDUMP = $(CROSS_COMPILE)objdump
# LOTs of includes # LOTs of includes
CFLAGS = -O2 -DDEBUG -g \ CFLAGS = -O2 -DDEBUG -g \
-I../../kernel/wbgen-regs \
-I$(LINUX)/include \ -I$(LINUX)/include \
-I$(LINUX)/arch/arm/mach-at91/include \ -I$(LINUX)/arch/arm/mach-at91/include \
-I../ptp-noposix/libptpnetif \ -I../ptp-noposix/libptpnetif \
......
userspace/tools/spll_dbg_proxy.c
View file @ 21076329
...@@ -22,8 +22,8 @@ ...@@ -22,8 +22,8 @@
#include <sys/socket.h> #include <sys/socket.h>
#include <arpa/inet.h> #include <arpa/inet.h>
#include "hw/fpga_regs.h" #include <fpga_io.h>
#include "softpll_regs.h" #include <regs/softpll-regs.h>
/* TCP Port to listen on */ /* TCP Port to listen on */
#define MY_PORT 12345 #define MY_PORT 12345
......
userspace/tools/wr_phytool.c
View file @ 21076329
...@@ -22,7 +22,9 @@ ...@@ -22,7 +22,9 @@
#include <linux/mii.h> #include <linux/mii.h>
#include "endpoint-regs.h" #include <regs/endpoint-regs.h>
#undef PACKED
#include "ptpd_netif.h" #include "ptpd_netif.h"
#include "rt_ipc.h" #include "rt_ipc.h"
......
userspace/wrsw_hal/Makefile
View file @ 21076329
...@@ -14,7 +14,7 @@ WR_LIB = $(WR_INSTALL_ROOT)/lib ...@@ -14,7 +14,7 @@ WR_LIB = $(WR_INSTALL_ROOT)/lib
CFLAGS = -g -Wall -DDEBUG -DRT_CLIENT\ CFLAGS = -g -Wall -DDEBUG -DRT_CLIENT\
-I../include -I../mini-rpc -I$(WR_INCLUDE) -I../include -I../mini-rpc -I$(WR_INCLUDE)
LDFLAGS = -L$(WR_INSTALL_ROOT)/lib -L../3rdparty/lib -L$(WR_LIB) \ LDFLAGS = -L$(WR_INSTALL_ROOT)/lib -L$(WR_LIB) \
-L../libswitchhw -L../mini-rpc \ -L../libswitchhw -L../mini-rpc \
-lminipc -llua -lm -ldl -lswitchhw -lminipc -llua -lm -ldl -lswitchhw
......
userspace/wrsw_hal/hal_ports.c
View file @ 21076329
...@@ -21,8 +21,8 @@ ...@@ -21,8 +21,8 @@
#include <pio.h> #include <pio.h>
#include <sfp_lib.h> #include <sfp_lib.h>
#include <hw/fpga_regs.h> #include <fpga_io.h>
#include <hw/endpoint_regs.h> #include <regs/endpoint-regs.h>
#include "wrsw_hal.h" #include "wrsw_hal.h"
#include "timeout.h" #include "timeout.h"
......
userspace/wrsw_rtud/rtu_drv.c
View file @ 21076329
...@@ -36,6 +36,7 @@ ...@@ -36,6 +36,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <stddef.h>
#include <unistd.h> #include <unistd.h>
#include <fcntl.h> #include <fcntl.h>
#include <stdlib.h> #include <stdlib.h>
...@@ -45,8 +46,8 @@ ...@@ -45,8 +46,8 @@
#include <switch_hw.h> #include <switch_hw.h>
#include <hal_client.h> #include <hal_client.h>
#include <hw/fpga_regs.h> #include <fpga_io.h>
#include <hw/rtu_regs.h> #include <regs/rtu-regs.h>
#include "rtu_drv.h" #include "rtu_drv.h"
#include "wr_rtu.h" #include "wr_rtu.h"
...@@ -122,26 +123,22 @@ void rtu_exit(void) ...@@ -122,26 +123,22 @@ void rtu_exit(void)
} }
static inline uint32_t rtu_rd(uint32_t reg) #define rtu_rd(reg) \
{ _fpga_readl(FPGA_BASE_RTU + offsetof(struct RTU_WB, reg))
return _fpga_readl(FPGA_BASE_RTU + reg);
}
static inline void rtu_wr(uint32_t reg, uint32_t value) #define rtu_wr(reg, val) \
{ _fpga_writel(FPGA_BASE_RTU + offsetof(struct RTU_WB, reg), val)
_fpga_writel(FPGA_BASE_RTU + reg, value);
}
static inline void write_pcr(int port, uint32_t pcr) static inline void write_pcr(int port, uint32_t pcr)
{ {
rtu_wr(RTU_REG_PSR, RTU_PSR_PORT_SEL_W(port)); rtu_wr(PSR, RTU_PSR_PORT_SEL_W(port));
rtu_wr(RTU_REG_PCR, pcr); rtu_wr(PCR, pcr);
} }
static inline uint32_t read_pcr(int port) static inline uint32_t read_pcr(int port)
{ {
rtu_wr(RTU_REG_PSR, RTU_PSR_PORT_SEL_W(port)); rtu_wr(PSR, RTU_PSR_PORT_SEL_W(port));
return rtu_rd(RTU_REG_PCR); return rtu_rd(PCR);
} }
// UFIFO // UFIFO
...@@ -152,7 +149,7 @@ static inline uint32_t read_pcr(int port) ...@@ -152,7 +149,7 @@ static inline uint32_t read_pcr(int port)
*/ */
int rtu_ufifo_is_empty(void) int rtu_ufifo_is_empty(void)
{ {
uint32_t csr = rtu_rd( RTU_REG_UFIFO_CSR); uint32_t csr = rtu_rd( UFIFO_CSR);
return RTU_UFIFO_CSR_EMPTY & csr; return RTU_UFIFO_CSR_EMPTY & csr;
} }
...@@ -164,7 +161,7 @@ int rtu_read_learning_queue_cnt(void) ...@@ -164,7 +161,7 @@ int rtu_read_learning_queue_cnt(void)
{ {
// Get counter from UFIFO Control-Status Register // Get counter from UFIFO Control-Status Register
// Fixme: USEDW returns 0 (FIFO overflow?) // Fixme: USEDW returns 0 (FIFO overflow?)
uint32_t csr = rtu_rd( RTU_REG_UFIFO_CSR); uint32_t csr = rtu_rd( UFIFO_CSR);
return RTU_UFIFO_CSR_USEDW_R(csr); return RTU_UFIFO_CSR_USEDW_R(csr);
} }
...@@ -195,11 +192,11 @@ int rtu_read_learning_queue(struct rtu_request *req) ...@@ -195,11 +192,11 @@ int rtu_read_learning_queue(struct rtu_request *req)
} }
// read data from mapped IO memory // read data from mapped IO memory
uint32_t r0 = rtu_rd( RTU_REG_UFIFO_R0); uint32_t r0 = rtu_rd( UFIFO_R0);
uint32_t r1 = rtu_rd( RTU_REG_UFIFO_R1); uint32_t r1 = rtu_rd( UFIFO_R1);
uint32_t r2 = rtu_rd( RTU_REG_UFIFO_R2); uint32_t r2 = rtu_rd( UFIFO_R2);
uint32_t r3 = rtu_rd( RTU_REG_UFIFO_R3); uint32_t r3 = rtu_rd( UFIFO_R3);
uint32_t r4 = rtu_rd( RTU_REG_UFIFO_R4); uint32_t r4 = rtu_rd( UFIFO_R4);
// Once read: if learning queue becomes empty again, enable UFIFO IRQ // Once read: if learning queue becomes empty again, enable UFIFO IRQ
...@@ -244,7 +241,7 @@ int rtu_read_learning_queue(struct rtu_request *req) ...@@ -244,7 +241,7 @@ int rtu_read_learning_queue(struct rtu_request *req)
int rtu_read_mfifo_cnt(void) int rtu_read_mfifo_cnt(void)
{ {
// Get counter from MFIFO Control-Status Register // Get counter from MFIFO Control-Status Register
uint32_t csr = rtu_rd( RTU_REG_MFIFO_CSR); uint32_t csr = rtu_rd( MFIFO_CSR);
return RTU_MFIFO_CSR_USEDW_R(csr); return RTU_MFIFO_CSR_USEDW_R(csr);
} }
...@@ -254,7 +251,7 @@ int rtu_read_mfifo_cnt(void) ...@@ -254,7 +251,7 @@ int rtu_read_mfifo_cnt(void)
*/ */
int rtu_mfifo_is_full(void) int rtu_mfifo_is_full(void)
{ {
uint32_t csr = rtu_rd( RTU_REG_MFIFO_CSR); uint32_t csr = rtu_rd( MFIFO_CSR);
return RTU_MFIFO_CSR_FULL & csr; return RTU_MFIFO_CSR_FULL & csr;
} }
...@@ -264,16 +261,16 @@ int rtu_mfifo_is_full(void) ...@@ -264,16 +261,16 @@ int rtu_mfifo_is_full(void)
*/ */
int rtu_mfifo_is_empty(void) int rtu_mfifo_is_empty(void)
{ {
uint32_t csr = rtu_rd( RTU_REG_MFIFO_CSR); uint32_t csr = rtu_rd( MFIFO_CSR);
return RTU_MFIFO_CSR_EMPTY & csr; return RTU_MFIFO_CSR_EMPTY & csr;
} }
static inline void flush_mfifo() static inline void flush_mfifo()
{ {
uint32_t gcr = rtu_rd (RTU_REG_GCR); uint32_t gcr = rtu_rd (GCR);
rtu_wr(RTU_REG_GCR, gcr | RTU_GCR_MFIFOTRIG); rtu_wr(GCR, gcr | RTU_GCR_MFIFOTRIG);
while(!rtu_rd(RTU_REG_GCR) & RTU_GCR_MFIFOTRIG); /* wait while the RTU is busy flushing the MFIFO */ while(!rtu_rd(GCR) & RTU_GCR_MFIFOTRIG); /* wait while the RTU is busy flushing the MFIFO */
} }
/** /**
...@@ -340,7 +337,7 @@ void rtu_clean_htab(void) ...@@ -340,7 +337,7 @@ void rtu_clean_htab(void)
*/ */
uint32_t rtu_read_agr_htab( uint32_t addr ) uint32_t rtu_read_agr_htab( uint32_t addr )
{ {
return rtu_rd( RTU_ARAM_BASE + 4*addr) ; return _fpga_readl(FPGA_BASE_RTU + RTU_ARAM_BASE + 4*addr) ;
} }
/** /**
...@@ -350,7 +347,7 @@ void rtu_clean_agr_htab(void) ...@@ -350,7 +347,7 @@ void rtu_clean_agr_htab(void)
{ {
int addr; int addr;
for(addr=0;addr < RTU_ARAM_WORDS;addr++) { for(addr=0;addr < RTU_ARAM_WORDS;addr++) {
rtu_wr(RTU_ARAM_BASE + 4*addr, 0x00000000); _fpga_writel(FPGA_BASE_RTU + RTU_ARAM_BASE + 4*addr, 0x00000000);
} }
} }
...@@ -365,7 +362,7 @@ void rtu_write_vlan_entry(uint32_t addr, struct vlan_table_entry *ent) ...@@ -365,7 +362,7 @@ void rtu_write_vlan_entry(uint32_t addr, struct vlan_table_entry *ent)
{ {
// printf("write_VLAN_ent: addr %x val %x\n", + RTU_VLAN_TAB + 4*addr, vlan_entry_word0_w(ent)); // printf("write_VLAN_ent: addr %x val %x\n", + RTU_VLAN_TAB + 4*addr, vlan_entry_word0_w(ent));
rtu_wr(RTU_VLAN_TAB_BASE + 4*addr, vlan_entry_word0_w(ent)); _fpga_writel(FPGA_BASE_RTU + RTU_VLAN_TAB_BASE + 4*addr, vlan_entry_word0_w(ent));
TRACE_DBG( TRACE_DBG(
TRACE_INFO, TRACE_INFO,
"write vlan entry: addr %x ent %08x %08x %08x %08x %08x", "write vlan entry: addr %x ent %08x %08x %08x %08x %08x",
...@@ -381,7 +378,7 @@ void rtu_write_vlan_entry(uint32_t addr, struct vlan_table_entry *ent) ...@@ -381,7 +378,7 @@ void rtu_write_vlan_entry(uint32_t addr, struct vlan_table_entry *ent)
void rtu_clean_vlan_entry( uint32_t addr ) void rtu_clean_vlan_entry( uint32_t addr )
{ {
// Value 0x80000000 sets drop field to 1 (VLAN entry not registered) // Value 0x80000000 sets drop field to 1 (VLAN entry not registered)
rtu_wr(RTU_VLAN_TAB_BASE + 4*addr, 0x80000000); _fpga_writel(FPGA_BASE_RTU + RTU_VLAN_TAB_BASE + 4*addr, 0x80000000);
} }
/** /**
...@@ -391,7 +388,7 @@ void rtu_clean_vlan(void) ...@@ -391,7 +388,7 @@ void rtu_clean_vlan(void)
{ {
int addr; int addr;
for (addr = 0; addr < NUM_VLANS; addr++) { for (addr = 0; addr < NUM_VLANS; addr++) {
rtu_wr(RTU_VLAN_TAB_BASE + 4*addr, 0x80000000); _fpga_writel(FPGA_BASE_RTU + RTU_VLAN_TAB_BASE + 4*addr, 0x80000000);
} }
} }
...@@ -403,8 +400,8 @@ void rtu_clean_vlan(void) ...@@ -403,8 +400,8 @@ void rtu_clean_vlan(void)
*/ */
void rtu_enable(void) void rtu_enable(void)
{ {
uint32_t gcr = rtu_rd( RTU_REG_GCR); uint32_t gcr = rtu_rd( GCR);
rtu_wr(RTU_REG_GCR, gcr | RTU_GCR_G_ENA); rtu_wr(GCR, gcr | RTU_GCR_G_ENA);
TRACE_DBG(TRACE_INFO,"updated gcr (enable): %x\n", gcr); TRACE_DBG(TRACE_INFO,"updated gcr (enable): %x\n", gcr);
} }
...@@ -413,8 +410,8 @@ void rtu_enable(void) ...@@ -413,8 +410,8 @@ void rtu_enable(void)
*/ */
void rtu_disable(void) void rtu_disable(void)
{ {
uint32_t gcr = rtu_rd( RTU_REG_GCR); uint32_t gcr = rtu_rd( GCR);
rtu_wr(RTU_REG_GCR, gcr & (~RTU_GCR_G_ENA)); rtu_wr(GCR, gcr & (~RTU_GCR_G_ENA));
TRACE_DBG(TRACE_INFO,"updated gcr (disable): %x\n", gcr); TRACE_DBG(TRACE_INFO,"updated gcr (disable): %x\n", gcr);
} }
...@@ -424,7 +421,7 @@ void rtu_disable(void) ...@@ -424,7 +421,7 @@ void rtu_disable(void)
*/ */
uint16_t rtu_read_hash_poly(void) uint16_t rtu_read_hash_poly(void)
{ {
uint32_t gcr = rtu_rd( RTU_REG_GCR); uint32_t gcr = rtu_rd( GCR);
return RTU_GCR_POLY_VAL_R(gcr); return RTU_GCR_POLY_VAL_R(gcr);
} }
...@@ -435,11 +432,11 @@ uint16_t rtu_read_hash_poly(void) ...@@ -435,11 +432,11 @@ uint16_t rtu_read_hash_poly(void)
void rtu_write_hash_poly(uint16_t hash_poly) void rtu_write_hash_poly(uint16_t hash_poly)
{ {
// Get current GCR // Get current GCR
uint32_t gcr = rtu_rd( RTU_REG_GCR); uint32_t gcr = rtu_rd( GCR);
// Clear previous hash poly and insert the new one // Clear previous hash poly and insert the new one
gcr = (gcr & (~RTU_GCR_POLY_VAL_MASK)) | RTU_GCR_POLY_VAL_W(hash_poly); gcr = (gcr & (~RTU_GCR_POLY_VAL_MASK)) | RTU_GCR_POLY_VAL_W(hash_poly);
// Update GCR // Update GCR
rtu_wr(RTU_REG_GCR, gcr ); rtu_wr(GCR, gcr );
TRACE_DBG(TRACE_INFO,"updated gcr (poly): %x\n", gcr); TRACE_DBG(TRACE_INFO,"updated gcr (poly): %x\n", gcr);
} }
...@@ -570,14 +567,14 @@ int rtu_set_unrecognised_behaviour_on_port(int port, int flag) ...@@ -570,14 +567,14 @@ int rtu_set_unrecognised_behaviour_on_port(int port, int flag)
static void write_mfifo_addr(uint32_t zbt_addr) static void write_mfifo_addr(uint32_t zbt_addr)
{ {
rtu_wr(RTU_REG_MFIFO_R0, RTU_MFIFO_R0_AD_SEL); rtu_wr(MFIFO_R0, RTU_MFIFO_R0_AD_SEL);
rtu_wr(RTU_REG_MFIFO_R1, zbt_addr); rtu_wr(MFIFO_R1, zbt_addr);
} }
static void write_mfifo_data(uint32_t word) static void write_mfifo_data(uint32_t word)
{ {
rtu_wr(RTU_REG_MFIFO_R0, RTU_MFIFO_R0_DATA_SEL); rtu_wr(MFIFO_R0, RTU_MFIFO_R0_DATA_SEL);
rtu_wr(RTU_REG_MFIFO_R1, word); rtu_wr(MFIFO_R1, word);
} }
// to marshall MAC entries // to marshall MAC entries
......
userspace/wrsw_rtud/rtu_fd.c
View file @ 21076329
...@@ -36,8 +36,8 @@ ...@@ -36,8 +36,8 @@
#include <unistd.h> #include <unistd.h>
#include <pthread.h> #include <pthread.h>
#include <hw/fpga_regs.h> #include <fpga_io.h>
#include <hw/rtu_regs.h> #include <regs/rtu-regs.h>
#include <trace.h> #include <trace.h>
......
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