libswitchhw: imported function ppsg_sync_external_pps() from the old svn repo

5011e937 · Tomasz Wlostowski · Alessandro Rubini · 125264a1 · 5011e937 · 5011e937
Commit 5011e937 authored Oct 12, 2011 by Tomasz Wlostowski Committed by Alessandro Rubini Oct 23, 2011
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pps_gen_regs.h userspace/include/hw/pps_gen_regs.h +10 -1

pps_gen.c userspace/libswitchhw/pps_gen.c +19 -0

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--- a/userspace/include/hw/pps_gen_regs.h
+++ b/userspace/include/hw/pps_gen_regs.h
@@ -3,7 +3,7 @@

  * File           : ../../../software/include/hw/pps_gen_regs.h
  * Author         : auto-generated by wbgen2 from wrsw_pps_gen.wb
-  * Created        : Sat Sep 11 22:22:55 2010
+  * Created        : Mon May  9 00:28:48 2011
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
@@ -14,6 +14,8 @@
 #ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
 #define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB

+#include <inttypes.h>
+
 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))
 #else
@@ -60,6 +62,11 @@
 /* definitions for register: UTC Adjustment register (least-significant part) */

 /* definitions for register: UTC Adjustment register (most-significant part) */
+
+/* definitions for register: External sync control register */
+
+/* definitions for field: Sync to external PPS input in reg: External sync control register */
+#define PPSG_ESCR_SYNC                        WBGEN2_GEN_MASK(0, 1)
 /* [0x0]: REG Control Register */
 #define PPSG_REG_CR 0x00000000
 /* [0x4]: REG Nanosecond counter register */
@@ -74,4 +81,6 @@
 #define PPSG_REG_ADJ_UTCLO 0x00000014
 /* [0x18]: REG UTC Adjustment register (most-significant part) */
 #define PPSG_REG_ADJ_UTCHI 0x00000018
+/* [0x1c]: REG External sync control register */
+#define PPSG_REG_ESCR 0x0000001c
 #endif
--- a/userspace/libswitchhw/pps_gen.c
+++ b/userspace/libswitchhw/pps_gen.c
@@ -61,3 +61,22 @@ int shw_pps_gen_busy()
 {
  return _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CR) & PPSG_CR_CNT_ADJ ? 0 : 1;
 }
+
+/* Syncs the PPS generator PPS with the externally provided signal. */
+int shw_pps_gen_sync_external_pps()
+{
+  TRACE(TRACE_INFO, "Syncing to external PPS..");
+    
+  _fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, 6);
+  _fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR, PPSG_ESCR_SYNC);
+        
+  /* fixme: waiting here is unstable. Probably a HW bug. */
+  /* fixme: re-phasing the AD9516 clock is also required */
+        
+/*  while(!(_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR) & PPSG_ESCR_SYNC))
+    {
+       sleep(1);
+    }*/
+	return 0;
+}
+                
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