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White Rabbit Switch - Software
Commit 50d73135 authored by Alessandro Rubini's avatar Alessandro Rubini
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wbgen-regs: removed spurious wb files

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wbgen-regs/dmpll_wb.wb deleted 100644 → 0
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral
{
name = "DMTD phase-shifting PLL";
description = "Main linear DMTD PLL controller (DMPLL).";
prefix = "DMPLL";
hdl_entity = "dmpll_wb_slave";
reg {
name = "DMPLL Control Register";
description = "DMPLL Control register";
prefix = "PCR";
field {
name = "DMPLL Enable";
description = "1: DMPLL is enabled \
0: DMPLL is disabled";
type = BIT;
prefix = "ENABLE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DMPLL Force Freq mode";
type = BIT;
prefix = "FORCE_F";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DAC serial clock select";
description = "Selects the DAC serial clock frequency: \
0: f = sysclk / 8 (~ 16 MHz) \
1: f = sysclk / 16 (~ 8 MHz) \
2: f = sysclk / 32 (~ 4 MHz) \
3: f = sysclk / 64 (~ 2 MHz) \
4: f = sysclk / 128 (~ 1 MHz) \
5: f = sysclk / 256 (~ 500 kHz) \
6: f = sysclk / 512 (~ 250 kHz) \
7: f = sysclk / 1024 (~ 125 kHz)";
prefix = "DAC_CLKSEL";
align = 4;
type = SLV;
size = 3;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reference clock input select";
description = "Index of active reference clock input (00 = IN0 ... 11 = IN3)";
align = 2;
size = 2;
type = SLV;
prefix = "REFSEL";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Phase shifter speed";
description = "Determines how fast the phase shifter works. The phase setpoint is increased or decreased by 1 every 64*PS_SPEED DMTD clock cycles";
size = 12;
type = SLV;
prefix = "PS_SPEED";
};
field {
name = "PLL Reset";
descritpion = "write 1: causes DMPLL reset\nwrite 0: no effect";
type = MONOSTABLE;
prefix = "SWRST";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
align=31;
};
};
reg {
name = "DMPLL Frequency Branch Gain Register";
description = "Register containing the PI gain factors for the frequency branch.";
prefix = "FBGR";
field {
name = "Proportional gain (Kp)";
prefix = "F_KP";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Integral gain (Ki)";
prefix = "F_KI";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DMPLL Phase Branch Gain Register";
prefix = "PBGR";
field {
name = "Proportional gain (Kp)";
prefix = "P_KP";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Integral gain (Ki)";
prefix = "P_KI";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DMPLL Lock Detect Control Register";
prefix = "LDCR";
field {
name = "Lock detect threshold";
prefix = "LD_THR";
description = "Maximum value of phase error that keeps the DMPLL locked";
type = SLV;
size = 12;
align = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Lock detect samples";
prefix = "LD_SAMP";
description = "Number of subsequent phase or frequency error samples smaller than LD_THR or frequency error samples in (-1, 1) after which the PLL assumes to be locked.";
type =SLV;
size = 12;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DMPLL Status Register";
description = "Register containing the current status of the DMPLL";
prefix = "PSR";
field {
name = "Frequency lock";
type = BIT;
prefix = "FREQ_LK";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Phase lock";
type = BIT;
prefix = "PHASE_LK";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Loss-of-lock indicator";
description = "read 0: PLL is locked\
read 1: PLL has lost the lock since the last poll of this bit\
write 0: no effect\
write 1: clears the field"
;
type = BIT;
prefix = "LOCK_LOST";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
fifo_reg {
name = "DMPLL Phase/Output record FIFO";
description = "A FIFO recording the phase/freq error, the DAC output and other PLL parameters for debugging/optimization purposes";
prefix = "RFIFO";
direction = CORE_TO_BUS;
size = 1024;
flags_bus = {FIFO_EMPTY};
flags_dev = {FIFO_FULL};
field {
name = "Freq/phase error";
description = "Current frequency/phase error value";
prefix = "ERR_VAL";
type = SLV;
size = 18;
};
field {
name = "Ref tag";
prefix = "TAG_REF";
type = SLV;
size = 18;
};
field {
name = "Feedback tag";
prefix = "TAG_FB";
type = SLV;
size = 18;
};
field {
name = "Freq/phase mode";
description = "1: frequency mode operation,\n 0: phase mode operation";
prefix = "FP_MODE";
type = BIT;
align = 31;
size = 1;
};
field {
name = "DAC output";
description = "Current DAC output value";
prefix = "DAC_VAL";
type = SLV;
size = 16;
align = 16;
};
};
};
function gen_dgcr(prefix, clockname)
local r =
reg {
name = "DMPLL Deglitcher Control Register for "..clockname.." clock";
description = "Register controlling the deglitcher for "..clockname.." clock DMTD channel";
prefix = "DGCR_"..prefix;
field {
name = "Low level stable threshold";
description = "Stable LOW input state detection threshold. The input to has to remain in LOW state for THR_LO DMTD clock cycles (with no glitches) for the deglitcher to detect a stable LOW state";
prefix = "THR_LO";
size = 12;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "High level stable threshold";
description = "Stable HIGH input state detection threshold. The input to has to remain in HIGH state for THR_HI DMTD clock cycles (with no glitches) for the deglitcher to detect a stable HIGH state";
prefix = "THR_HI";
size = 12;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Glitch threshold";
description = "Number of accummulated glitches after which the deglitcher identifies a rising edge in the input signal";
prefix = "THR_GLITCH";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
table.insert(periph, r);
end
function gen_pscr(prefix, clockname)
local r =
reg {
name = "DMPLL Phase Shifter Control Register for "..clockname.." clock";
description = "Register controlling the phase shift between the feedback clock and "..clockname.." input";
prefix = "PSCR_"..prefix;
field {
name = "Current Phase Shift";
description = "Read: returns the current phase shift with respect to feedback clock (in DMTDCLK clock cycles)\
Write: sets the new phase shift value. Cannot be written when PS_BUSY is active (the new value is ignored)";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Phase Shifter Busy";
description = "0: phase shifter for clock "..clockname.."is idle\
1: phase shifter is busy";
prefix = "BUSY";
align=31;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
table.insert(periph, r);
end
gen_dgcr("IN0", "Reference input 0");
gen_dgcr("IN1", "Reference input 1");
gen_dgcr("IN2", "Reference input 2");
gen_dgcr("IN3", "Reference input 3");
gen_dgcr("FB", "TCXO clock");
gen_pscr("IN0", "Reference input 0");
gen_pscr("IN1", "Reference input 1");
gen_pscr("IN2", "Reference input 2");
gen_pscr("IN3", "Reference input 3");
wbgen-regs/ep_wishbone_controller.wb deleted 100644 → 0
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wbgen-regs/hpll_wb.wb deleted 100644 → 0
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral
{
name = "DMTD Helper PLL";
description = "PLL controller for generating the DMTD offset clock.";
prefix = "HPLL";
hdl_entity = "hpll_wb_slave";
reg {
name = "HPLL Control Register";
description = "HPLL Control register";
prefix = "PCR";
field {
name = "PLL Enable";
description = "1: PLL is enabled \
0: PLL is disabled";
type = BIT;
prefix = "ENABLE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL Force Freq mode";
type = BIT;
prefix = "FORCE_F";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DAC serial clock select";
description = "Selects the DAC serial clock frequency: \
0: f = refclk / 8 (~ 16 MHz) \
1: f = refclk / 16 (~ 8 MHz) \
2: f = refclk / 32 (~ 4 MHz) \
3: f = refclk / 64 (~ 2 MHz) \
4: f = refclk / 128 (~ 1 MHz) \
5: f = refclk / 256 (~ 500 kHz) \
6: f = refclk / 512 (~ 250 kHz) \
7: f = refclk / 1024 (~ 125 kHz)";
prefix = "DAC_CLKSEL";
align = 4;
type = SLV;
size = 3;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Phase detector gating period";
description = "Gating period for the phase detector: \
0: period = 1024 \
1: period = 2048 \
2: period = 4096 \
3: period = 8192 \
4: period = 16384 \
5: period = 32768 \
6: period = 65536 \
7: period = 131072";
prefix = "PD_GATE";
type = SLV;
size = 3;
align = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reference clock input select";
description = "00: local reference (from TCXO)\
01: uplink 0 recovered clock\
10: uplink 1 recovered clock";
size = 2;
type = SLV;
prefix = "REFSEL";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PLL Reset";
descritpion = "write 1: causes PLL reset\nwrite 0: no effect";
type = MONOSTABLE;
prefix = "SWRST";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
align=31;
};
};
reg {
name = "HPLL Divider Register";
description = "Register controlling the frequency PLL frequency divider. The output frequency is f_ref * (DIV_FB / DIV_REF)";
prefix = "DIVR";
field {
name = "Reference divider";
prefix = "DIV_REF";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Feedback divider";
prefix = "DIV_FB";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "HPLL Frequency Branch Gain Register";
description = "Register containing the PI gain factors for the frequency branch.";
prefix = "FBGR";
field {
name = "Proportional gain (Kp)";
prefix = "F_KP";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Integral gain (Ki)";
prefix = "F_KI";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "HPLL Phase Branch Gain Register";
prefix = "PBGR";
field {
name = "Proportional gain (Kp)";
prefix = "P_KP";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Integral gain (Ki)";
prefix = "P_KI";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "HPLL Lock Detect Control Register";
prefix = "LDCR";
field {
name = "Phase Lock detect threshold";
prefix = "LD_THR";
description = "A maximum time between bang-bang PD phase error sign changes that keeps the PLL locked";
type = SLV;
size = 8;
align = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Lock detect samples";
prefix = "LD_SAMP";
description = "Number of subsequent phase error samples smaller than LD_THR or frequency error samples in (-1, 1) after which the PLL assumes to be locked.";
type =SLV;
size = 8;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "HPLL Frequency branch control register";
prefix = "FBCR";
field {
name = "Frequency detector gating period";
description = "Gating period for the frequency detector: \
0: period = 16384 \
1: period = 32768 \
2: period = 65536 \
3: period = 131072 \
4: period = 262144 \
5: period = 524288 \
6: period = 1048576 \
7: period = 2097152";
prefix = "FD_GATE";
type = SLV;
size = 3;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
align =4;
};
field {
name = "Frequency error setpoint";
description = "Value of desired frequency error in the lock state. Computed as: f_err = FD_GATE[real value] * (1 - (N / (N+DELTA)))";
prefix = "FERR_SET";
align = 4;
size = 12;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "HPLL Status Register";
description = "Register containing the current status of the PLL";
prefix = "PSR";
field {
name = "Frequency lock";
type = BIT;
prefix = "FREQ_LK";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Phase lock";
type = BIT;
prefix = "PHASE_LK";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Loss-of-lock indicator";
description = "read 0: PLL is locked\
read 1: PLL has lost the lock since the last poll of this bit\
write 0: no effect\
write 1: clears the field";
type = BIT;
prefix = "LOCK_LOST";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
fifo_reg {
name = "HPLL Phase/Output record FIFO";
description = "A FIFO recording the phase/freq error, the DAC output and other PLL parameters for debugging/optimization purposes";
prefix = "RFIFO";
direction = CORE_TO_BUS;
size = 1024;
flags_bus = {FIFO_EMPTY};
flags_dev = {FIFO_FULL};
field {
name = "Freq/phase error";
description = "Current frequency/phase error value";
prefix = "ERR_VAL";
type = SLV;
size = 12;
};
field {
name = "Freq/phase mode";
description = "1: frequency mode operation,\n 0: phase mode operation";
prefix = "FP_MODE";
type = BIT;
align = 15;
size = 1;
};
field {
name = "DAC output";
description = "Current DAC output value";
prefix = "DAC_VAL";
type = SLV;
size = 16;
align = 16;
};
};
};
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wbgen-regs/mini_nic.wb deleted 100644 → 0
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Mini NIC for WhiteRabbit";
description = "Simple, embedded WhiteRabbit-compiliant Network Interface Controller (NIC) for use in WhiteRabbit embedded receivers";
prefix = "minic";
hdl_entity = "minic_wb_slave";
reg {
name = "miNIC Control Register";
prefix = "MCR";
field {
name = "TX DMA start";
prefix = "TX_START";
description = "write 1: starts the DMA transmission of TX descriptors placed in the DMA buffer, write 0: no effect";
type = MONOSTABLE;
};
field {
name = "TX DMA idle";
prefix = "TX_IDLE";
description = "1: TX DMA engine is idle.\n0: TX DMA engine is busy, don't touch the buffer";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX DMA error";
prefix = "TX_ERROR";
description = "1: an error occured during the TX DMA transfer. The address at which the error occured is kept in TX_ADDR register";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA ready";
prefix = "RX_READY";
description = "1: RX buffer contains at least one packet";
type = BIT;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA buffer full";
prefix = "RX_FULL";
description = "1: RX buffer is full";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA enable";
prefix = "RX_EN";
description = "1: RX buffer is allocated and initialized by the host, the miNIC can receive packets\n0: RX buffer not ready, reception is disabled";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX DMA Address";
description = "Address of the start of TX buffer:\
read: base address of the last transmitted TX descriptor\
write: base address of the first descriptor to transmit";
prefix = "TX_ADDR";
field {
name = "TX DMA buffer address";
size = 24;
align = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "RX DMA Address";
description = "Address of the start of RX buffer:\
read: address of the last received RX descriptor\
write: base address of the RX buffer";
prefix = "RX_ADDR";
field {
name = "RX DMA buffer address";
size = 24;
align = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "RX buffer size register";
description = "Number of available 32-bit words in the RX buffer";
prefix = "RX_AVAIL";
field {
name = "RX available words";
size = 24;
align = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
fifo_reg {
name = "TX timestamp FIFO";
prefix = "TSFIFO";
size = 16;
direction = CORE_TO_BUS;
flags_bus = {FIFO_EMPTY};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "Timestamp value";
prefix = "TSVAL";
size = 32;
type = SLV;
};
field {
name = "Port ID";
prefix = "PID";
size = 5;
type = SLV;
};
field {
name = "Frame ID";
prefix = "FID";
size = 16;
type = SLV;
};
};
reg {
name = "Debug register";
prefix = "DBGR";
field {
name = "interrupt counter";
prefix = "IRQ_CNT";
size = 24;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "status of wb_irq_o line";
prefix = "WB_IRQ_VAL";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
irq {
name = "TX DMA interrupt";
trigger = LEVEL_1;
ack_line = true;
mask_line = true;
prefix = "TX";
};
irq {
name = "RX DMA interrupt";
trigger = LEVEL_1;
ack_line = true;
prefix = "RX";
};
irq {
name = "TX timestamp available";
trigger = LEVEL_1;
prefix = "TXTS";
};
};
\ No newline at end of file
wbgen-regs/pcs_regs.wb deleted 100644 → 0
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wbgen-regs/rev_id.wb deleted 100644 → 0
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peripheral {
name = "Wishbone firmware/revision ID";
prefix = "ID";
hdl_entity = "wb_rev_id";
reg {
name = "Magic number register";
prefix = "MAGIC";
field {
name = "Magic number identifying the revision ID block";
type = CONSTANT;
size = 32;
value = 0xdeadbeef;
};
};
reg {
name = "Firmware Revision Register";
prefix = "REVID";
field {
name = "Revision of this firmware";
type = CONSTANT;
size = 32;
value = 76;
};
};
reg {
name = "Firmware Variant Hash Register";
prefix = "HASH";
field {
name = "Hash value of the firmware name";
type = CONSTANT;
size = 32;
value = 0x0678743c;
};
};
};
\ No newline at end of file
wbgen-regs/rtu_testunit_wb.wb deleted 100644 → 0
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-- -*- Mode: LUA; tab-width: 2 -*-
NUM_QUEUES = 10;
peripheral {
name = "RTU testing unit";
description = "RTU testing unit";
hdl_entity = "rtu_testunit_wb";
prefix = "RTT";
reg {
name = "FIFO Polling Register";
description = "Each bit indicates the presence of responses in the correspinding RFIFO";
prefix = "FPR";
field {
name = "Non-empty FIFOs";
size = NUM_QUEUES;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
irq {
name = "FIFO Not Empty";
prefix = "NEMPTY";
description = "Triggered when there are RTU responses in any of the RFIFOs";
trigger = LEVEL_1;
};
};
queue_template = {
fifo_reg {
name = "Response FIFO for RTU channel ";
prefix = "RFIFO_CH";
direction = CORE_TO_BUS;
size = 1024;
flags_dev = {FIFO_EMPTY};
field {
name = "Destination port mask";
prefix = "DPM";
type = SLV;
size = NUM_QUEUES+1;
};
field {
name = "Final priority";
prefix = "PRIO";
type = SLV;
size = 3;
};
field {
name = "Drop packet flag";
prefix = "DROP";
type = BIT;
};
};
};
function generate_resp_queues(n)
local i;
for i=1,n do
local T=deepcopy(queue_template);
foreach_reg({TYPE_FIFO}, function(r)
r.name = r.name..(i-1);
r.prefix = r.prefix..(i-1);
end, T);
table_join(periph, T);
end
end
generate_resp_queues(NUM_QUEUES);
\ No newline at end of file
wbgen-regs/wb_vic.wb deleted 100644 → 0
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Vectored Interrupt Controller (VIC)";
description = "Module implementing a 2 to 32-input prioritized interrupt controller with internal interrupt vector storage support.";
prefix = "VIC";
hdl_entity = "wb_slave_vic";
reg {
name = "VIC Control Register";
prefix = "CTL";
field {
name = "VIC Enable";
description = "1: enables VIC operation\n0: disables VIC operation";
prefix = "ENABLE";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "VIC output polarity";
description = "1: IRQ output is active high\n0: IRQ output is active low";
prefix = "POL";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Raw Interrupt Status Register";
prefix = "RISR";
field {
name = "Raw interrupt status";
description = "Each bit reflects the current state of corresponding IRQ input line.\nread 1: interrupt line is currently active\nread 0: interrupt line is inactive";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Interrupt Enable Register";
prefix = "IER";
field {
name = "Enable IRQ";
description = "Write 1: enables interrupt associated with written bit\nWrite 0: no effect";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "Interrupt Disable Register";
prefix = "IDR";
field {
name = "Disable IRQ";
description = "Write 1: enables interrupt associated with written bit\nWrite 0: no effect";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "Interrupt Mask Register";
prefix = "IMR";
field {
name = "IRQ disabled/enabled";
description = "Read 1: interrupt associated with bitfield is enabled\nRead 0: interrupt is disabled";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Vector Address Register";
prefix = "VAR";
field {
name = "Vector Address";
description = "Address of pending interrupt vector, read from Interrupt Vector Table";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Software Interrupt Register";
description = "Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.";
prefix = "SWIR";
field {
name = "SWI interrupt mask";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "End Of Interrupt Acknowledge Register";
prefix = "EOIR";
field {
name = "End of Interrupt";
description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s).";
type = PASS_THROUGH;
size = 32;
};
};
ram {
name = "Interrupt Vector Table";
description = "Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register.";
prefix = "IVT_RAM";
size = 32;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
\ No newline at end of file
wbgen-regs/wr_nic.wb deleted 100644 → 0
View file @ b05d585a
This diff is collapsed.
wbgen-regs/wrsw_calibrator_dmtd.wb deleted 100644 → 0
View file @ b05d585a
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "DMTD PHY Calibrator";
prefix = "dpc";
hdl_entity = "dmtd_calibrator_wb";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Enable";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Compare clock select";
prefix = "IN_SEL";
type = SLV;
size = 4;
align = 8;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Status register";
prefix = "SR";
field {
name = "Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
};
wbgen-regs/wrsw_pps_gen.wb deleted 100644 → 0
View file @ b05d585a
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Switch PPS generator and RTC";
description = "Unit generating PPS signals and acting as a UTC real-time clock";
hdl_entity = "pps_gen_wb";
prefix = "ppsg";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Reset counter";
description = "write 1: resets the counter\
write 0: no effect";
prefix = "CNT_RST";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "Enable counter";
description = "1: PPS counter is enabled";
prefix = "CNT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Adjust offset";
description = "write 1: Starts adjusting PPS/UTC offsets by adding the values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers to the current PPS counter value. These registers need to be programmed prior to update.\
write 0: no effect\
read 0: adjustment operation is done\
read 1: adjustment operation is in progress";
prefix = "CNT_ADJ";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "Set time";
description = "write 1: Sets the UTC/PPS counter to values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers";
prefix = "CNT_SET";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "PPS Pulse width";
description = "Width of generated PPS pulses in 125 MHz refernce clock cycles";
prefix = "PWIDTH";
size = 28;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock= "refclk_i";
};
};
reg {
name = "Nanosecond counter register";
description = "Nanosecond part of current time, expressed as number of 125 MHz reference clock cycles";
prefix = "CNTR_NSEC";
field {
name = "Nanosecond counter";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (least-significant part)";
description = "Lower 32 bits of current UTC time";
prefix = "CNTR_UTCLO";
field {
name = "UTC Counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (most-significant part)";
description = "Highest 8 bits of current UTC time";
prefix = "CNTR_UTCHI";
field {
name = "UTC Counter";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "Nanosecond adjustment register";
description = "Adjustment value for nanosecond counter";
prefix = "ADJ_NSEC";
field {
name = "Nanosecond adjustment";
type = PASS_THROUGH;
size = 28;
};
};
reg {
name = "UTC Adjustment register (least-significant part)";
description = "Lower 32 bits of adjustment value for UTC";
prefix = "ADJ_UTCLO";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "UTC Adjustment register (most-significant part)";
description = "Highest 8 bits of adjustment value for UTC";
prefix = "ADJ_UTCHI";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 8;
};
};
};
wbgen-regs/wrsw_txtsu.wb deleted 100644 → 0
View file @ b05d585a
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Shared TX Timestamping Unit (TXTSU)";
prefix="txtsu";
hdl_entity="wrsw_txtsu_wb";
-- TXTSU shared FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf";
name = "Timestamp FIFO";
description = "This FIFO holds the TX packet timestamps gathered from all switch endpoints. Each entry contains a single timestamp value consisting of 2 numbers:\
- VAL_R - the timestamp taken at rising clock edge. This is the main timestamp value\
- VAL_F - few LSBs of timestamp taken at falling clock edge. It's used in conjunction with VAL_R to determine if the timestamp has been taken\
properly (there was no metastability/setup/hold violation)\
Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
- FID - Frame identifier assigned by the NIC\
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "Rising edge timestamp";
descritpion = "Timestamp value taken on rising clock edge (full word)";
prefix = "val_r";
type = SLV;
size = 28;
};
field {
name = "Falling edge timestamp";
description = "Timestamp value taken on falling clock edge (few LSBs)";
prefix = "val_f";
type = SLV;
size = 4;
};
field {
name ="Physical port ID";
description = "Identifier of the TXTSU port to which came the timestamp. There may be multiple timestamps sharing the same FID value for broadcast/multicast packets.";
prefix = "pid";
type = SLV;
size = 5;
align= 16;
};
field {
name = "Frame ID";
description = "OOB Frame Identifier. Used to associate the timestamp value with transmitted packet.";
prefix = "fid";
type = SLV;
size = 16;
align = 16;
};
};
-- TXTSU interrupts
irq {
name = "TXTSU fifo not-empty";
description = "Interrupt active when TXTSU shared FIFO contains any timestamps.";
prefix = "nempty";
trigger = LEVEL_0;
};
};
\ No newline at end of file
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