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White Rabbit Switch - Software
Commit 6bef87d2 authored by Adam Wujek's avatar Adam Wujek 💬
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userspace/snmpd: use softpll_export.h instead of softpll_ng.h 

Use softpll_export.h instead of softpll_ng.h to handle stats exports from
the softpll.

For details, please check the following commit in the wrpc-sw repo
softpll: move stats defines to new file softpll_export.h

Additionally two new align state values:
ALIGN_STATE_WAIT_CLKIN
ALIGN_STATE_WAIT_PLOCK
Signed-off-by: Adam Wujek's avatarAdam Wujek <adam.wujek@cern.ch>
parent 6e68c985
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Showing with 123 additions and 188 deletions
ppsi @ 25d7dbe4
Subproject commit 18b1a039696b217779b94172350cfd26e452504e
Subproject commit 25d7dbe4fb2b735c4c9c1f4102950bd78e9e9f7e
userspace/snmpd/WR-SWITCH-MIB.txt
View file @ 6bef87d2
......@@ -1048,7 +1048,7 @@ wrsSpllMode OBJECT-TYPE
MAX-ACCESS read-only
STATUS current
DESCRIPTION
"Mode of Soft PLL (values taken from softpll_ng.h)"
"Mode of Soft PLL (values taken from softpll_export.h, wrpc-sw repo)"
::= { wrsSpllStatusGroup 1 }
wrsSpllIrqCnt OBJECT-TYPE
......@@ -1075,7 +1075,7 @@ wrsSpllSeqState OBJECT-TYPE
MAX-ACCESS read-only
STATUS current
DESCRIPTION
"Sequence state of Soft PLL (values taken from file softpll_ng.c in wrpc-sw repo)"
"Sequence state of Soft PLL (values taken from file softpll_export.h, wrpc-sw repo)"
::= { wrsSpllStatusGroup 3 }
wrsSpllAlignState OBJECT-TYPE
......@@ -1088,12 +1088,14 @@ wrsSpllAlignState OBJECT-TYPE
compensateDelay(5),
locked(6),
startAlignment(7),
startMain(8)
startMain(8),
waitClkIn(9),
waitPlock(10)
}
MAX-ACCESS read-only
STATUS current
DESCRIPTION
"Align state of Soft PLL (values taken from file spll_external.c in wrpc-sw repo)"
"Align state of Soft PLL (values taken from file softpll_export.h, wrpc-sw repo)"
::= { wrsSpllStatusGroup 4 }
wrsSpllHlock OBJECT-TYPE
......
userspace/snmpd/softpll_export.h 0 → 100644
View file @ 6bef87d2
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2010 - 2013 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/* softpll_export.h: public SoftPLL stats API header */
#ifndef __SOFTPLL_EXPORT_H
#define __SOFTPLL_EXPORT_H
#include <stdint.h>
/* SoftPLL operating modes, for mode parameter of spll_init(). */
/* Grand Master - lock to 10 MHz external reference */
#define SPLL_MODE_GRAND_MASTER 1
/* Free running master - 125 MHz refrence free running, DDMTD locked to it */
#define SPLL_MODE_FREE_RUNNING_MASTER 2
/* Slave mode - 125 MHz reference locked to one of the input clocks */
#define SPLL_MODE_SLAVE 3
/* Disabled mode: SoftPLL inactive */
#define SPLL_MODE_DISABLED 4
#define SEQ_START_EXT 1
#define SEQ_WAIT_EXT 2
#define SEQ_START_HELPER 3
#define SEQ_WAIT_HELPER 4
#define SEQ_START_MAIN 5
#define SEQ_WAIT_MAIN 6
#define SEQ_DISABLED 7
#define SEQ_READY 8
#define SEQ_CLEAR_DACS 9
#define SEQ_WAIT_CLEAR_DACS 10
#define AUX_DISABLED 1
#define AUX_LOCK_PLL 2
#define AUX_ALIGN_PHASE 3
#define AUX_READY 4
#define ALIGN_STATE_EXT_OFF 0
#define ALIGN_STATE_START 1
#define ALIGN_STATE_INIT_CSYNC 2
#define ALIGN_STATE_WAIT_CSYNC 3
#define ALIGN_STATE_START_ALIGNMENT 7
#define ALIGN_STATE_WAIT_SAMPLE 4
#define ALIGN_STATE_COMPENSATE_DELAY 5
#define ALIGN_STATE_LOCKED 6
#define ALIGN_STATE_START_MAIN 8
#define ALIGN_STATE_WAIT_CLKIN 9
#define ALIGN_STATE_WAIT_PLOCK 10
#define SPLL_STATS_VER 2
/* info reported through .stat section */
/* due to endiannes problem strings has to be 4 bytes alligned */
struct spll_stats {
int magic; /* 0x5b1157a7 = SPLLSTAT ?;)*/
int ver; /* version of the structure */
int sequence; /* sequence number, so the host can retry */
int mode;
int irq_cnt;
int seq_state;
int align_state;
int H_lock;
int M_lock;
int H_y, M_y;
int del_cnt;
int start_cnt;
char commit_id[32];
char build_date[16];
char build_time[16];
};
extern struct spll_stats stats;
#endif /* __SOFTPLL_EXPORT_H */
userspace/snmpd/softpll_ng.h deleted 100644 → 0
View file @ 6e68c985
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2010 - 2013 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/* softpll_ng.h: public SoftPLL API header */
#ifndef __SOFTPLL_NG_H
#define __SOFTPLL_NG_H
#include <stdint.h>
/* SoftPLL operating modes, for mode parameter of spll_init(). */
/* Grand Master - lock to 10 MHz external reference */
#define SPLL_MODE_GRAND_MASTER 1
/* Free running master - 125 MHz refrence free running, DDMTD locked to it */
#define SPLL_MODE_FREE_RUNNING_MASTER 2
/* Slave mode - 125 MHz reference locked to one of the input clocks */
#define SPLL_MODE_SLAVE 3
/* Disabled mode: SoftPLL inactive */
#define SPLL_MODE_DISABLED 4
/* Shortcut for 'channels' parameter in various API functions to perform operation on all channels */
#define SPLL_ALL_CHANNELS 0xffffffff
/* Aux clock flags */
#define SPLL_AUX_ENABLED (1<<0) /* Locking the particular aux channel to the WR reference is enabled */
#define SPLL_AUX_LOCKED (1<<1) /* The particular aux clock is already locked to WR reference */
/* Phase detector types */
#define SPLL_PD_DDMTD 0
#define SPLL_PD_BANGBANG 1
/* Channels for spll_measure_frequency() */
#define SPLL_OSC_REF 0
#define SPLL_OSC_DMTD 1
#define SPLL_OSC_EXT 2
/* Note on channel naming:
- ref_channel means a PHY recovered clock input. There can be one (as in WR core) or more (WR switch).
- out_channel means an output channel, which represents PLL feedback signal from a local, tunable oscillator. Every SPLL implementation
has at least one output channel, connected to the 125 / 62.5 MHz transceiver (WR) reference. This channel has always
index 0 and is compared against all reference channels by the phase tracking mechanism.
*/
/* PUBLIC API */
/*
Initializes the SoftPLL to work in mode (mode). Extra parameters depend on choice of the mode:
- for SPLL_MODE_GRAND_MASTER: non-zero (align_pps) value enables realignment of the WR reference rising edge to the
rising edge of 10 MHz external clock that comes immediately after a PPS pulse
- for SPLL_MODE_SLAVE: (ref_channel) indicates the reference channel to which we are locking our PLL.
*/
void spll_init(int mode, int ref_channel, int align_pps);
/* Disables the SoftPLL and cleans up stuff */
void spll_shutdown();
/* Returns number of reference and output channels implemented in HW. */
void spll_get_num_channels(int *n_ref, int *n_out);
/* Starts locking output channel (out_channel) */
void spll_start_channel(int out_channel);
/* Stops locking output channel (out_channel) */
void spll_stop_channel(int out_channel);
/* Returns non-zero if output channel (out_channel) is locked to a WR reference */
int spll_check_lock(int out_channel);
/* Sets phase setpoint for given output channel. */
void spll_set_phase_shift(int out_channel, int32_t value_picoseconds);
/* Retreives the current phase shift and desired setpoint for given output channel */
void spll_get_phase_shift(int out_channel, int32_t *current, int32_t *target);
/* Returns non-zero if the given output channel is busy phase shifting to a new preset */
int spll_shifter_busy(int out_channel);
/* Returns phase detector type used by particular output channel. There are two phase detectors available:
- DDMTD: locks only 62.5 / 125 MHz. Provides independent phase shift control for each output.
- Bang-Bang: locks to any frequency that is a result of rational (M/N) multiplication of the reference frequency.
The frequency can be set by spll_set_aux_frequency(). BB detector follows phase setpoint of channel 0 (WR reference),
there is no per-output shift control.
*/
int spll_get_phase_detector_type(int out_channel);
/* Sets the aux clock freuency when a BB detector is in use.
Must be called prior to spll_start_channel(). If the frequency is out of available range,
returns negative value */
int spll_set_aux_frequency(int out_channel, int32_t frequency);
/* Enables/disables phase tracking on channel (ref_channel). Phase is always measured between
the WR local reference (out_channel 0) and ref_channel */
void spll_enable_ptracker(int ref_channel, int enable);
/* Reads tracked phase shift value for given reference channel */
int spll_read_ptracker(int ref_channel, int32_t *phase_ps, int *enabled);
/* Calls non-realtime update state machine. Must be called regularly (although
* it is not time-critical) in the main loop of the program if aux clocks or
* external reference are used in the design. */
void spll_update();
/* Returns the status of given aux clock output (SPLL_AUX_) */
int spll_get_aux_status(int out_channel);
const char *spll_get_aux_status_string(int channel);
/* Debug/testing functions */
/* Returns how many time the PLL has de-locked since last call of spll_init() */
int spll_get_delock_count();
void spll_show_stats(void);
/* Sets VCXO tuning DAC corresponding to output (out_channel) to a given value */
void spll_set_dac(int out_channel, int value);
/* Returns current DAC sample value for output (out_channel) */
int spll_get_dac(int out_channel);
void check_vco_frequencies();
#define SPLL_STATS_VER 2
/* info reported through .stat section */
/* due to endiannes problem strings has to be 4 bytes alligned */
struct spll_stats {
int magic; /* 0x5b1157a7 = SPLLSTAT ?;)*/
int ver; /* version of the structure */
int sequence; /* sequence number, so the host can retry */
int mode;
int irq_cnt;
int seq_state;
int align_state;
int H_lock;
int M_lock;
int H_y, M_y;
int del_cnt;
int start_cnt;
char commit_id[32];
char build_date[16];
char build_time[16];
};
/* This only exists in wr-switch, but we should use it always */
extern struct spll_stats stats;
#endif // __SOFTPLL_NG_H
userspace/snmpd/wrsSpllStatusGroup.c
View file @ 6bef87d2
#include "wrsSnmp.h"
#include "softpll_export.h"
#include "wrsSpllStatusGroup.h"
#include "softpll_ng.h"
#include "snmp_mmap.h"
#define FPGA_SPLL_STAT 0x10006800
......
userspace/snmpd/wrsSpllStatusGroup.h
View file @ 6bef87d2
#ifndef WRS_SPLL_STATUS_GROUP_H
#define WRS_SPLL_STATUS_GROUP_H
#include "softpll_export.h"
#define WRSSPLLSTATUS_CACHE_TIMEOUT 5
#define WRSSPLLSTATUS_OID WRS_OID, 7, 3, 2
/* values taken from softpll_ng.h */
#define WRS_SPLL_MODE_GRAND_MASTER 1
#define WRS_SPLL_MODE_MASTER 2 /* free running master */
#define WRS_SPLL_MODE_SLAVE 3
/* values taken from softpll_export.h */
#define WRS_SPLL_MODE_GRAND_MASTER SPLL_MODE_GRAND_MASTER
#define WRS_SPLL_MODE_MASTER SPLL_MODE_FREE_RUNNING_MASTER /* free running master */
#define WRS_SPLL_MODE_SLAVE SPLL_MODE_SLAVE
#define WRS_SPLL_MODE_DISABLED SPLL_MODE_DISABLED
/* values taken from file spll_external.c in wrpc-sw repo */
#define WRS_SPLL_ALIGN_STATE_EXT_OFF 0
#define WRS_SPLL_ALIGN_STATE_START 1
#define WRS_SPLL_ALIGN_STATE_INIT_CSYNC 2
#define WRS_SPLL_ALIGN_STATE_WAIT_CSYNC 3
#define WRS_SPLL_ALIGN_STATE_START_ALIGNMENT 7
#define WRS_SPLL_ALIGN_STATE_WAIT_SAMPLE 4
#define WRS_SPLL_ALIGN_STATE_COMPENSATE_DELAY 5
#define WRS_SPLL_ALIGN_STATE_LOCKED 6
#define WRS_SPLL_ALIGN_STATE_START_MAIN 8
#define WRS_SPLL_ALIGN_STATE_EXT_OFF ALIGN_STATE_EXT_OFF
#define WRS_SPLL_ALIGN_STATE_START ALIGN_STATE_START
#define WRS_SPLL_ALIGN_STATE_INIT_CSYNC ALIGN_STATE_INIT_CSYNC
#define WRS_SPLL_ALIGN_STATE_WAIT_CSYNC ALIGN_STATE_WAIT_CSYNC
#define WRS_SPLL_ALIGN_STATE_START_ALIGNMENT ALIGN_STATE_START_ALIGNMENT
#define WRS_SPLL_ALIGN_STATE_WAIT_SAMPLE ALIGN_STATE_WAIT_SAMPLE
#define WRS_SPLL_ALIGN_STATE_COMPENSATE_DELAY ALIGN_STATE_COMPENSATE_DELAY
#define WRS_SPLL_ALIGN_STATE_LOCKED ALIGN_STATE_LOCKED
#define WRS_SPLL_ALIGN_STATE_START_MAIN ALIGN_STATE_START_MAIN
#define WRS_SPLL_ALIGN_STATE_WAIT_CLKIN ALIGN_STATE_WAIT_CLKIN
#define WRS_SPLL_ALIGN_STATE_WAIT_PLOCK ALIGN_STATE_WAIT_PLOCK
/* values taken from file softpll_ng.c in wrpc-sw repo */
#define WRS_SPLL_SEQ_STATE_START_EXT 1
#define WRS_SPLL_SEQ_STATE_WAIT_EXT 2
#define WRS_SPLL_SEQ_STATE_START_HELPER 3
#define WRS_SPLL_SEQ_STATE_WAIT_HELPER 4
#define WRS_SPLL_SEQ_STATE_START_MAIN 5
#define WRS_SPLL_SEQ_STATE_WAIT_MAIN 6
#define WRS_SPLL_SEQ_STATE_DISABLED 7
#define WRS_SPLL_SEQ_STATE_READY 8
#define WRS_SPLL_SEQ_STATE_CLEAR_DACS 9
#define WRS_SPLL_SEQ_STATE_WAIT_CLEAR_DACS 10
#define WRS_SPLL_SEQ_STATE_START_EXT SEQ_START_EXT
#define WRS_SPLL_SEQ_STATE_WAIT_EXT SEQ_WAIT_EXT
#define WRS_SPLL_SEQ_STATE_START_HELPER SEQ_START_HELPER
#define WRS_SPLL_SEQ_STATE_WAIT_HELPER SEQ_WAIT_HELPER
#define WRS_SPLL_SEQ_STATE_START_MAIN SEQ_START_MAIN
#define WRS_SPLL_SEQ_STATE_WAIT_MAIN SEQ_WAIT_MAIN
#define WRS_SPLL_SEQ_STATE_DISABLED SEQ_DISABLED
#define WRS_SPLL_SEQ_STATE_READY SEQ_READY
#define WRS_SPLL_SEQ_STATE_CLEAR_DACS SEQ_CLEAR_DACS
#define WRS_SPLL_SEQ_STATE_WAIT_CLEAR_DACS SEQ_WAIT_CLEAR_DACS
struct wrsSpllStatus_s {
int32_t wrsSpllMode;
......
userspace/snmpd/wrsSpllVersionGroup.c
View file @ 6bef87d2
#include "wrsSnmp.h"
#include "wrsSpllVersionGroup.h"
#include "softpll_ng.h"
#include "softpll_export.h"
#include "snmp_mmap.h"
#define FPGA_SPLL_STAT 0x10006800
......
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