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White Rabbit Switch - Software
Commit 98c1b44a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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libswitchhw/pps_gen.c: removed fixed 8ns divisor from shw_pps_gen_adjust_nsec()

parent 604235b0
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Showing with 3 additions and 20 deletions
userspace/libswitchhw/pps_gen.c
View file @ 98c1b44a
......@@ -31,16 +31,16 @@ int shw_pps_gen_init()
_fpga_writel(FPGA_BASE_PPS_GEN + 0x1c, 0x6); /* enable PPS output */
}
/* Adjusts the nanosecond (125 MHz refclk cycle) counter by atomically adding (how_much). */
/* Adjusts the nanosecond (refclk cycle) counter by atomically adding (how_much) cycles. */
int shw_pps_gen_adjust_nsec(int32_t how_much)
{
uint32_t cr;
TRACE(TRACE_INFO, "AdjustPPS: %d nanoseconds", how_much);
TRACE(TRACE_INFO, "AdjustPPS: %d cycles", how_much);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCLO, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCHI, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, ( how_much / 8 ));
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, how_much);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_WIDTH) | PPSG_CR_CNT_ADJ);
}
......@@ -63,21 +63,4 @@ int shw_pps_gen_busy()
return _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CR) & PPSG_CR_CNT_ADJ ? 0 : 1;
}
/* Syncs the PPS generator PPS with the externally provided signal. */
int shw_pps_gen_sync_external_pps()
{
TRACE(TRACE_INFO, "Syncing to external PPS..");
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, 6);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR, PPSG_ESCR_SYNC);
/* fixme: waiting here is unstable. Probably a HW bug. */
/* fixme: re-phasing the AD9516 clock is also required */
/* while(!(_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR) & PPSG_ESCR_SYNC))
{
sleep(1);
}*/
return 0;
}
\ No newline at end of file
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