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Commit a92d86e4 authored by Alessandro Rubini's avatar Alessandro Rubini
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kernel modules: initial fix of NIC for V3

parent dc258a8e
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Showing with 62 additions and 71 deletions
kernel/wr_nic/device.c
View file @ a92d86e4
......@@ -64,7 +64,7 @@ static int __devexit wrn_remove(struct platform_device *pdev)
/* This helper is used by probe below */
static int __devinit __wrn_map_resources(struct platform_device *pdev)
{
int n, i = 0;
int i = 0;
struct resource *res;
void __iomem *ptr;
struct wrn_dev *wrn = pdev->dev.platform_data;
......@@ -81,10 +81,9 @@ static int __devinit __wrn_map_resources(struct platform_device *pdev)
return -ENOMEM;
}
/* Hack: find the block number and fill the array */
n = __FPGA_BASE_TO_NR(res->start);
pr_debug("Remapped %08x (block %i) to %p\n",
res->start, n, ptr);
wrn->bases[n] = ptr;
res->start, i, ptr);
wrn->bases[i] = ptr;
i++; /* next please */
}
......@@ -116,9 +115,9 @@ static int __devinit wrn_probe(struct platform_device *pdev)
if ( (err = __wrn_map_resources(pdev)) )
goto out;
wrn->regs = wrn->bases[WRN_BLOCK_NIC];
wrn->txtsu_regs = wrn->bases[WRN_BLOCK_TSTAMP];
wrn->ppsg_regs = wrn->bases[WRN_BLOCK_PPSG];
wrn->regs = wrn->bases[WRN_FB_NIC];
wrn->txtsu_regs = wrn->bases[WRN_FB_TS];
wrn->ppsg_regs = wrn->bases[WRN_FB_PPSG];
wrn->txd = ((void *)wrn->regs) + 0x80; /* was: TX1_D1 */
wrn->rxd = ((void *)wrn->regs) + 0x100; /* was: RX1_D1 */
wrn->databuf = (void *)wrn->regs + offsetof(struct NIC_WB, MEM);
......@@ -148,11 +147,13 @@ static int __devinit wrn_probe(struct platform_device *pdev)
/* The ep structure is filled before calling ep_probe */
ep = netdev_priv(netdev);
ep->wrn = wrn;
ep->ep_regs = wrn->bases[WRN_FIRST_EP + i];
ep->ep_regs = wrn->bases[WRN_FB_EP]; /* FIXME: works for 1EP */
//printk("ep %p, regs %i = %p\n", ep, i, ep->ep_regs);
ep->ep_number = i;
#if 0 /* FIXME: UPlink or not? */
if (i < WRN_NR_UPLINK)
set_bit(WRN_EP_IS_UPLINK, &ep->ep_flags);
#endif
/* The netdevice thing is registered from the endpoint */
err = wrn_endpoint_probe(netdev);
......
kernel/wr_nic/module.c
View file @ a92d86e4
......@@ -23,28 +23,18 @@
static struct wrn_dev wrn_dev;
/* The WRN_RES_ names are defined in the header file. Each block 64kB */
#define __RES(name) { \
.start = FPGA_BASE(name), \
.end = FPGA_BASE(name) + FPGA_BLOCK_SIZE-1, \
#define __RES(name_) { \
.start = FPGA_BASE_ ## name_, \
.end = FPGA_BASE_ ## name_ + FPGA_SIZE_ ## name_ - 1, \
.flags = IORESOURCE_MEM \
}
/* Not all the blocks are relevant to this driver, only list the used ones */
static struct resource wrn_resources[] = {
[WRN_RES_MEM_EP_UP0] = __RES( EP_UP0 ),
[WRN_RES_MEM_EP_UP1] = __RES( EP_UP1 ),
[WRN_RES_MEM_EP_DP0] = __RES( EP_DP0 ),
[WRN_RES_MEM_EP_DP1] = __RES( EP_DP1 ),
[WRN_RES_MEM_EP_DP2] = __RES( EP_DP2 ),
[WRN_RES_MEM_EP_DP3] = __RES( EP_DP3 ),
[WRN_RES_MEM_EP_DP4] = __RES( EP_DP4 ),
[WRN_RES_MEM_EP_DP5] = __RES( EP_DP5 ),
[WRN_RES_MEM_EP_DP6] = __RES( EP_DP6 ),
[WRN_RES_MEM_EP_DP7] = __RES( EP_DP7 ),
[WRN_RES_MEM_PPSG] = __RES( PPSG ),
[WRN_RES_MEM_CALIBRATOR]= __RES( CALIBRATOR ),
[WRN_RES_MEM_NIC] = __RES( NIC ),
[WRN_RES_MEM_TSTAMP] = __RES( TSTAMP )
__RES( NIC ),
__RES( EP ),
__RES( TS ),
__RES( PPSG ),
};
#undef __RES
......
kernel/wr_nic/nic-hardware.h
View file @ a92d86e4
......@@ -12,62 +12,62 @@
#define __WR_NIC_HARDWARE_H__
/* Our host CPU is this one, no way out of it */
#include <mach/at91sam9263.h>
//#include <mach/at91sam9263.h>
#define REFCLK_FREQ 125000000
/* The interrupt is one of those managed by our WRVIC device */
#define WRN_IRQ_BASE 192
#define WRN_IRQ_PPSG (WRN_IRQ_BASE + 0)
#define WRN_IRQ_NIC (WRN_IRQ_BASE + 1)
#define WRN_IRQ_RTU (WRN_IRQ_BASE + 2)
#define WRN_IRQ_RTUT (WRN_IRQ_BASE + 3)
#define WRN_IRQ_TSTAMP (WRN_IRQ_BASE + 4)
#define WRN_IRQ_NIC (WRN_IRQ_BASE + 0)
#define WRN_IRQ_TSTAMP (WRN_IRQ_BASE + 1) /* FIXME: not there */
//#define WRN_IRQ_PPSG (WRN_IRQ_BASE + )
//#define WRN_IRQ_RTU (WRN_IRQ_BASE + )
//#define WRN_IRQ_RTUT (WRN_IRQ_BASE + )
/*
* V3 Memory map, temporarily (Jan 2012)
*
* 0x00000 - 0x1ffff: RT Subsystem
* 0x00000 - 0x0ffff: RT Subsystem Program Memory (16 - 64 kB)
* 0x10000 - 0x100ff: RT Subsystem UART
* 0x10100 - 0x101ff: RT Subsystem SoftPLL-adv
* 0x10200 - 0x102ff: RT Subsystem SPI Master
* 0x10300 - 0x103ff: RT Subsystem GPIO
* 0x20000 - 0x3ffff: NIC
* 0x20000 - 0x20fff NIC control regs and descriptor area
* 0x28000 - 0x2bfff NIC packet buffer (16k)
* 0x40000 - 0x4ffff: Endpoints
* 0x40000 + N * 0x200 Endpoint N control registers
* 0x50000 - 0x50fff: VIC
* 0x51000 - 0x51fff: Tstamp unit
* 0x52000 - 0x52fff: PPS gen
*/
/* This is the base address of all the FPGA regions (EBI1, CS0) */
#define FPGA_BASE_ADDRESS 0x70000000
/* The memory map is split in several blocks, each of them 64kB */
#define FPGA_BLOCK_SIZE 0x10000 /* for ioremap */
#define __FPGA_BLOCK_TO_ADDR(block) \
(FPGA_BASE_ADDRESS + (block) * FPGA_BLOCK_SIZE)
#define FPGA_BASE_NIC 0x10020000
#define FPGA_SIZE_NIC 0x00010000
#define FPGA_BASE_EP 0x10040000
#define FPGA_SIZE_EP 0x00010000
#define FPGA_BASE_VIC 0x10050000
#define FPGA_SIZE_VIC 0x00001000
#define FPGA_BASE_TS 0x10051000
#define FPGA_SIZE_TS 0x00001000
#define FPGA_BASE_PPSG 0x10052000
#define FPGA_SIZE_PPSG 0x00001000
/* I number fpga blocks, to handle all the base addresses as an array */
enum fpga_blocks {
WRN_BLOCK_REVID = 0x00, /* Not used here */
WRN_BLOCK_GPIO = 0x01, /* Not used here */
WRN_BLOCK_SPIM = 0x02, /* Not used here */
WRN_BLOCK_VIC = 0x03, /* Separate module */
WRN_BLOCK_EP_UP0 = 0x04,
WRN_BLOCK_EP_UP1 = 0x05,
WRN_BLOCK_EP_DP0 = 0x06,
WRN_BLOCK_EP_DP1 = 0x07,
WRN_BLOCK_EP_DP2 = 0x08,
WRN_BLOCK_EP_DP3 = 0x09,
WRN_BLOCK_EP_DP4 = 0x0a,
WRN_BLOCK_EP_DP5 = 0x0b,
WRN_BLOCK_EP_DP6 = 0x0c,
WRN_BLOCK_EP_DP7 = 0x0d,
WRN_BLOCK_PPSG = 0x0e, /* pps.c */
WRN_BLOCK_CALIBRATOR = 0x0f, /* dmtd.c */
WRN_BLOCK_RTU = 0x10, /* Separate driver */
WRN_BLOCK_RTU_TESTUNIT = 0x11, /* Separate driver */
WRN_BLOCK_NIC = 0x12,
WRN_BLOCK_TSTAMP = 0x13, /* timestamp.c */
WRN_NBLOCKS /* number of blocks, for array size */
WRN_FB_NIC,
WRN_FB_EP,
WRN_FB_VIC, /* not mapped here (but in vic.ko) */
WRN_FB_TS,
WRN_FB_PPSG,
WRN_NR_OF_BLOCKS,
};
/* In addition to the above enumeration, mark out endpoints */
#define WRN_NR_ENDPOINTS 10
#define WRN_FIRST_EP WRN_BLOCK_EP_UP0
#define WRN_LAST_EP WRN_BLOCK_EP_DP7
#define WRN_NR_UPLINK (WRN_BLOCK_EP_DP0 - WRN_BLOCK_EP_UP0)
/* Hardware addresses are derived from the block numbers */
#define FPGA_BASE(name) __FPGA_BLOCK_TO_ADDR(WRN_BLOCK_ ## name)
/* And this bad thing exists to get the block from the address */
#define __FPGA_BASE_TO_NR(add) (((add) - FPGA_BASE_ADDRESS) / FPGA_BLOCK_SIZE)
/* In addition to the above enumeration, mark out endpoints (FIXME: 1 only) */
#define WRN_NR_ENDPOINTS 1
#define WRN_FIRST_EP WRN_BLOCK_EP_UP0
#define WRN_LAST_EP WRN_FIRST_EP
//#define WRN_NR_UPLINK (WRN_BLOCK_EP_DP0 - WRN_BLOCK_EP_UP0)
/* 8 tx and 8 rx descriptors */
#define WRN_NR_DESC 8
......
kernel/wr_nic/wr-nic.h
View file @ a92d86e4
......@@ -66,7 +66,7 @@ struct wrn_desc_pending {
*/
struct wrn_dev {
/* Base addresses. It's easier with an array, but not all are used */
void __iomem *bases[WRN_NBLOCKS];
void __iomem *bases[WRN_NR_OF_BLOCKS];
struct NIC_WB __iomem *regs; /* shorthand for NIC-block registers */
struct TXTSU_WB __iomem *txtsu_regs; /* ... and the same for TXTSU */
......
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