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White Rabbit Switch - Software
Commit b81a5d0e authored by Alessandro Rubini's avatar Alessandro Rubini
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Merge branch 'v3-rc1' into v3

parents b1f76342 479ab055
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Showing with 24702 additions and 14834 deletions
.gitignore
View file @ b81a5d0e
......@@ -7,3 +7,6 @@
modules.order
.tmp_versions
Module.symvers
.cproject
.project
.settings
.gitmodules 0 → 100644
View file @ b81a5d0e
[submodule "userspace/ptp-noposix"]
path = userspace/ptp-noposix
url = git://gnudd.com/ptp-noposix.git
[submodule "userspace/mini-rpc"]
path = userspace/mini-rpc
url = git://github.com/a-rubini/mini-rpc.git
binaries/g45memtest
View file @ b81a5d0e
No preview for this file type
build/download-info
View file @ b81a5d0e
......@@ -127,5 +127,6 @@ uClibc-0.9.32.tar.bz2 cfcb6c25d8ebe12817499d8749ee8ae1 \
zlib-1.2.5.tar.bz2 be1e89810e66150f5b0327984d8625a0 \
http://kent.dl.sourceforge.net/sourceforge/libpng/zlib-1.2.5.tar.bz2
wrs3-gw.tar.gz 339414ba4d26ee4d50ddb36284377860 \
http://www.ohwr.org/attachments/download/1371/wrs3-gw.tar.gz
build/flash-wrs
View file @ b81a5d0e
#!/bin/sh
# A script to compile the usb loader, possibly changing the mac address
showhelp()
{
echo "Usage: $0 [options] MAC [DEV]\n"
echo "MAC:\t MAC address in hexadecimal seperated by ':' (i.e, AB:CD:EF:01:23:45)"
echo "DEV:\t The usb device (by default it is /dev/ttyACM0)"
echo "Options: "
echo "\t-h|--help\t\t Show this help message"
echo "\t-m|--memmode\t\t can be: default, df (dataflash), nf (nandflash), test."
echo "\t-e \t\t\t Completely erase the memory (Can erase your configuration)"
echo "\t--build\t\t\t Use file that you have build in the WRS_OUTPUT_DIR"
echo "\t--test\t\t\t Use file for testing the switch (not available)"
echo "\t--silent\t\t Don't ask MAC or S/N and use default 02:0B:AD:C0:FF:EE"
echo ""
exit 0
}
checkExit()
{
err=0;
if [ $1 ]; then
if [ -f $1 ]; then
return 0;
else
echo "Can't find $1" >& 2;
fi
else
echo "varname not set"
fi
exit 1
}
modifyMAC()
{
origin=$1
new=$2
cp $origin $new
# check & change mac address
X="[0-9a-fA-F][0-9a-fA-F]"
while true; do
if echo $MAC | grep "^${X}:${X}:${X}:${X}:${X}:${X}\$" > /dev/null; then
sed -i "s/02:0B:AD:C0:FF:EE/$MAC/" $new
echo "MAC is now: $MAC"
return 0
else
if [ "x$MAC" != "x" ]; then
echo "$0: Invalid MAC address \"$MAC\"" >&2;
fi
if [ $silent ]; then
return 1;
fi
read -p "Enter MAC (XX:XX:XX:XX:XX:XX): " MAC
fi
done
}
# Sanity checks
if [ -d ./usb-loader ]; then true; else
......@@ -8,54 +67,91 @@ if [ -d ./usb-loader ]; then true; else
exit 1
fi
err=0;
if [ -f ./binaries/at91bootstrap.bin ]; then true; else err=1; fi
if [ -f ./binaries/barebox.bin ]; then true; else err=1; fi
# build flasher itself
if CC=cc make -s -C usb-loader; then true; else
echo "$0: Error compiling usb-loader" >&2; exit 1;
fi
if [ $err -eq 1 ]; then
echo "$0: Can't find either ./binaries/at91bootstrap.bin" >& 2
echo "$0: or ./binaries/barebox.bin" >& 2
exit 1
# Check if atmel sam-ba is find by lusb
lsusb | grep "at91sam SAMBA" > /dev/null
if [ $? -gt "0" ]; then
echo "Did not find the sam-ba monitor in lsusb....\nPlease check that the Dataflash is short-circuited!"
exit 1;
fi
# parse command line
DEV="/dev/ttyACM0"
MAC=""
DEV=""
FLAGS=""
at91bs="./binaries/at91bootstrap.bin"
barebox="./binaries/barebox.bin"
kernel="${WRS_OUTPUT_DIR}/images/zImage"
rootfs="${WRS_OUTPUT_DIR}/images/wrs-image.jffs2.img"
while [ $# -ge 1 ]; do
case $1 in
/* ) DEV="$1"; shift ;;
-b|--build)
at91bs=${WRS_OUTPUT_DIR}/images/at91bootstrap.bin;
barebox=${WRS_OUTPUT_DIR}/images/barebox.bin
kernel=${WRS_OUTPUT_DIR}/images/zImage
rootfs=${WRS_OUTPUT_DIR}/images/wrs-image.jffs2.img
shift;;
-h|--help) showhelp; shift;;
-m|--memmode) memmode="$2"; shift; shift;;
--silent) silent=1; shift;;
/* ) DEV="-s $1"; shift ;;
*:* ) MAC="$1"; shift ;;
-*) FLAGS="${FLAGS} $1"; shift;;
* ) echo "$0: Invalid argument \"$1\"" >&2; exit 1;;
esac
done
# check mac address
if [ "x$MAC" != "x" ]; then
X="[0-9a-fA-F][0-9a-fA-F]"
if echo $MAC | grep "^${X}:${X}:${X}:${X}:${X}:${X}\$" > /dev/null; then
true
else
echo "$0: Invalid MAC address \"$MAC\"" >&2; exit 1;
fi
## Selecting the running memmode
if [ "x$memmode" = "xdf" ]; then
df=1
elif [ "x$memmode" = "xnf" ]; then
nf=1
elif [ "x$memmode" = "xtest" ]; then
test=1
else
df=1
nf=1
fi
# build flasher itself
if CC=cc make -s -C usb-loader; then true; else
echo "$0: Error compiling usb-loader" >&2; exit 1;
## Flashing DataFlash
if [ $df ]; then
checkExit $at91bs
checkExit $barebox
Tbarebox=$(mktemp /tmp/barebox.XXXXXX)
modifyMAC ${barebox} ${Tbarebox}
./usb-loader/mch_flasher -m df $FLAGS $DEV ${at91bs} 0 ${Tbarebox} 33792
fi
# cat binaries to temp file. Increase size of at91boot (0x8400)
T=$(mktemp /tmp/wrs-flash.XXXXXX)
cat binaries/at91bootstrap.bin /dev/zero | dd bs=1 count=33792 > $T \
2> /dev/null
cat binaries/barebox.bin >> $T
## Flashing NANDFlash
if [ $nf ]; then
checkExit $kernel
checkExit $rootfs
./usb-loader/mch_flasher -m nand $FLAGS $DEV ${kernel} 0x00100000 ${rootfs} 0x04000000
fi
## Loading in DDR
if [ $test ]; then
checkExit $barebox
checkExit $kernel
checkExit $rootfs
Tbarebox=$(mktemp /tmp/barebox.XXXXXX)
modifyMAC ${barebox} ${Tbarebox}
# change the mac address if so requested
if [ "$MAC" != "x$MAC" ]; then
sed -i "s/02:0B:AD:C0:FF:EE/$MAC/" $T
./usb-loader/mch_flasher -m ddr $FLAGS $DEV ${Tbarebox} 0x0 ${kernel} 0x1000000 ${rootfs} 0x2000000
fi
# flash it (msc...)
(cd usb-loader && ./mch_flasher $T $DEV)
#rm -f $T
\ No newline at end of file
build/scripts/wrs_build_buildroot
View file @ b81a5d0e
......@@ -78,13 +78,10 @@ make oldconfig || wrs_die "buildroot config"
buildrootdir=$(/bin/pwd)
# the download dir in the config file is already set to ../../downloads
# However, to be safe, make a symlink for its default place, in case
# a custom config file is used
cd $buildrootdir
test -d dl || ln -sf $WRS_DOWNLOAD_DIR dl
# We don't want CC to be pre-set at this point (some of us do :)
unset CC
wrs_echo "Compiling buildroot"
make || wrs_die "buildroot compilation"
# tell to buildroot to use our download directory
make BUILDROOT_DL_DIR=$WRS_DOWNLOAD_DIR || wrs_die "buildroot compilation"
build/scripts/wrs_build_gateware 0 → 100755
View file @ b81a5d0e
#!/bin/bash
# check variables, like all scripts herein do
WRS_SCRIPT_NAME=$(basename $0)
. ${WRS_BASE_DIR}/scripts/wrs_functions
wrs_check_vars WRS_OUTPUT_DIR
wrs_echo "--- Deploying FPGA firmware"
mkdir -p ${WRS_OUTPUT_DIR}/images/wr
mkdir -p ${WRS_OUTPUT_DIR}/images/wr/lib
mkdir -p ${WRS_OUTPUT_DIR}/images/wr/lib/firmware
echo "$WRS_HW_DIR"
if [ "$WRS_HW_DIR" != "" ]; then
cp ${WRS_HW_DIR}/syn/scb_8ports/scb_top_synthesis.bin ${WRS_OUTPUT_DIR}/images/wr/lib/firmware/8ports_mb.bin
cp ${WRS_HW_DIR}/rt/rt_cpu.bin ${WRS_OUTPUT_DIR}/images/wr/lib/firmware/rt_cpu.bin
else
tarname=wrs3-gw.tar.gz
wrs_download $tarname
tar xzf $WRS_DOWNLOAD_DIR/$tarname -C ${WRS_OUTPUT_DIR}/images/wr/lib/firmware
fi
build/scripts/wrs_build_kernel
View file @ b81a5d0e
......@@ -47,4 +47,10 @@ make oldconfig || wrs_die "kernel config"
make $WRS_MAKE_J zImage modules || wrs_die "kernel compilation"
cp arch/$ARCH/boot/zImage $(find . -name '*.ko') $WRS_OUTPUT_DIR/images
mkdir -p $WRS_OUTPUT_DIR/images/lib
mkdir -p $WRS_OUTPUT_DIR/images/lib/modules
mkdir -p $WRS_OUTPUT_DIR/images/lib/modules/2.6.39
mkdir -p $WRS_OUTPUT_DIR/images/lib/modules/2.6.39/kernel
cp $(find . -name '*.ko') $WRS_OUTPUT_DIR/images/lib/modules/2.6.39/kernel
cp arch/$ARCH/boot/zImage $WRS_OUTPUT_DIR/images
build/scripts/wrs_build_modules
View file @ b81a5d0e
......@@ -22,4 +22,8 @@ cd $WRS_BASE_DIR/../kernel
make $WRS_MAKE_J || wrs_die "white rabbit kernel modules"
mkdir -p $WRS_OUTPUT_DIR/images
cp $(find . -name \*.ko) $WRS_OUTPUT_DIR/images
mkdir -p $WRS_OUTPUT_DIR/images/wr/
mkdir -p $WRS_OUTPUT_DIR/images/wr/lib
mkdir -p $WRS_OUTPUT_DIR/images/wr/lib/modules/
cp $(find . -name \*.ko) $WRS_OUTPUT_DIR/images/wr/lib/modules
build/scripts/wrs_build_ptp_noposix
View file @ b81a5d0e
......@@ -9,35 +9,15 @@ fi
wrs_check_vars WRS_OUTPUT_DIR WRS_DOWNLOAD_DIR CROSS_COMPILE
wrs_echo "--- PTP daemon (noposix repository)"
wrs_echo "--- PTP daemon (noposix repository as a submodule)"
mkdir -p $WRS_DOWNLOAD_DIR/ptp || wrs_die "mkdir downloads/ptp"
cd $WRS_DOWNLOAD_DIR/ptp
# checkout, in case the user didn't do that
cd ${WRS_BASE_DIR}/..
git submodule init -q
git submodule update -q
cd userspace/ptp-noposix
make clean
# checkout repository
if [ -d .git ]; then
git checkout v3 || (cd $WRS_DOWNLOAD_DIR && rm -rf ptp)
fi
# check again, as the above step may have removed stuff
mkdir -p $WRS_DOWNLOAD_DIR/ptp || wrs_die "mkdir downloads/ptp"
cd $WRS_DOWNLOAD_DIR/ptp
if [ -d .git ]; then
wrs_echo "Using local git repository (previous clone)"
else
wrs_echo "Checking out git repository"
git init
git remote add gnudd git://gnudd.com/ptp-noposix.git
git fetch gnudd
git checkout -b v3 gnudd/v3
fi
# to avoid building in the "download" place, copy it to the build place
cd "$WRS_OUTPUT_DIR/build"
dirname="ptp-noposix"
rm -rf "$dirname"
cp -a "$WRS_DOWNLOAD_DIR/ptp" "$dirname"
cd "$dirname"
# we need LINUX and CROSS_COMPILE. The latter is there for sure
if [ "x$LINUX" == "x" ]; then
export LINUX="$WRS_OUTPUT_DIR/build/linux-2.6.39"
......@@ -48,8 +28,7 @@ install -d "$WRS_OUTPUT_DIR/images/wr/bin"
install -d "$WRS_OUTPUT_DIR/images/wr/lib"
install -d "$WRS_OUTPUT_DIR/images/wr/include"
install ptpd "$WRS_OUTPUT_DIR/images/wr/bin"
install libwripc.a libptpnetif.a "$WRS_OUTPUT_DIR/images/wr/lib"
install libwripc/wr_ipc.h "$WRS_OUTPUT_DIR/images/wr/include"
install libptpnetif.a "$WRS_OUTPUT_DIR/images/wr/lib"
install libptpnetif/ptpd_netif.h "$WRS_OUTPUT_DIR/images/wr/include"
install libptpnetif/hal_client.h "$WRS_OUTPUT_DIR/images/wr/include"
......
build/scripts/wrs_build_userspace
View file @ b81a5d0e
......@@ -19,6 +19,13 @@ mkdir -p $installdir || wrs_die "mkdir images/wr"
# This time build is done in-place, but the output is a tree in images/wr.
# Some of the makefiles inside use
export LINUX="$WRS_OUTPUT_DIR/build/linux-2.6.39"
cd $sourcedir && make
# mini-rpc is an external package, it has no wr-specific install
install -d $installdir/lib
install mini-rpc/*.a $installdir/lib
cd $sourcedir && make install WR_INSTALL_ROOT="$installdir"
build/scripts/wrs_build_wraprootfs
View file @ b81a5d0e
......@@ -2,6 +2,7 @@
# check variables, like all scripts herein do
WRS_SCRIPT_NAME=$(basename $0)
if [ -z "$WRS_BASE_DIR" ]; then
echo "$0: Plesae set WRS_BASE_DIR" >& 2
exit 1
......@@ -24,7 +25,9 @@ rootfs_vanilla="$WRS_OUTPUT_DIR/build/buildroot-2011.11/output/target"
rootfs_override="$WRS_BASE_DIR/../userspace/rootfs_override"
TMPSCRIPT=$(mktemp /tmp/rootfs-script.XXXXXX)
ROOTFS_IMAGE="$WRS_OUTPUT_DIR/images/wrs-image.cpio.gz"
ROOTFS_IMAGE_CPIO="$WRS_OUTPUT_DIR/images/wrs-image.cpio.gz"
ROOTFS_IMAGE_TGZ="$WRS_OUTPUT_DIR/images/wrs-image.tar.gz"
ROOTFS_IMAGE_JFFS2="$WRS_OUTPUT_DIR/images/wrs-image.jffs2"
cat > $TMPSCRIPT << EOF
rm -r -f $TMPFS
......@@ -32,11 +35,10 @@ mkdir -p $TMPFS/wr
cp -r $rootfs_vanilla/* $TMPFS
cp -r $WRS_OUTPUT_DIR/images/wr/* $TMPFS/wr
cp -r $WRS_OUTPUT_DIR/images/lib/* $TMPFS/lib
rm -f $TMPFS/etc/init.d/*
cp -r $rootfs_override/* $TMPFS
mkdir -p $TMPFS/wr/lib/modules
cp $WRS_OUTPUT_DIR/images/*ko $TMPFS/wr/lib/modules
rm -rf $TMPFS/dev
(cd $TMPFS && tar xzf $DEVTAR)
(cd $TMPFS && ln -s sbin/init .)
......@@ -51,7 +53,9 @@ chmod g-w $TMPFS/root $TMPFS/root/.ssh
chown -R root:root $TMPFS/root
chown -R root:root $TMPFS/etc/dropbear
(cd "$TMPFS" && find . | cpio -o -H newc | gzip) > $ROOTFS_IMAGE
(cd "$TMPFS" && find . | cpio -o -H newc | gzip) > $ROOTFS_IMAGE_CPIO
(cd "$TMPFS" && tar cz .> $ROOTFS_IMAGE_TGZ)
/usr/sbin/mkfs.jffs2 --little-endian --eraseblock=0x20000 -n --pad -d $TMPFS -o $ROOTFS_IMAGE_JFFS2.img
EOF
......
build/wrs_build-all
View file @ b81a5d0e
......@@ -113,7 +113,8 @@ wrs_build_step 04-kernel wrs_build_kernel
wrs_build_step 05-modules wrs_build_modules
wrs_build_step 06-ptp-noposix wrs_build_ptp_noposix
wrs_build_step 07-wrs-userspace wrs_build_userspace
wrs_build_step 08-wrap-rootfs wrs_build_wraprootfs
wrs_build_step 08-wrs-gateware wrs_build_gateware
wrs_build_step 09-wrap-rootfs wrs_build_wraprootfs
if $failed_step; then
wrs_die "One or more build steps failed"
......
doc/wrs-build.in
View file @ b81a5d0e
......@@ -240,9 +240,11 @@ did not add the new archives in there because of their size.
@node Downloading Files
@section Downloading Files
Every downloaded file is saved to the @code{download} directory, you should
Every downloaded file is saved to the @code{download} directory
(if set @code{WRS_DOWNLOAD_DIR} else the default
@code{$WRS_OUPUT_DIR/downloads}). You should
arrange not to remove that directory when you recompile over and over
during development. I chose to make the first
during development. I chose to make the first
script download everything, because I think this eases development in a
way: you first wait a while but can tell download errors from other
issues, and then you can build it all even without a network connection.
......@@ -326,22 +328,26 @@ step takes only a pair of seconds to verify the checksums:
@c FIXME: example
@smallexample
2012-01-12 18:59:04: --- Downloading all files
2012-01-12 18:59:06: --- Buildroot compiler and filesystem
2012-01-12 18:59:06: Uncompressing buildroot
2012-01-12 18:59:06: Patching buildroot
2012-01-12 18:59:06: Reconfiguring buildroot
2012-01-12 18:59:07: Compiling buildroot
2012-01-12 19:14:16: --- AT91Boot
2012-01-12 19:14:16: Patching AT91Boot
2012-01-12 19:14:16: Building AT91Boot
2012-01-12 19:14:17: --- Barebox
2012-01-12 19:14:17: Patching Barebox
2012-01-12 19:14:17: Building Barebox
2012-01-12 19:14:25: --- Linux kernel for switch
2012-01-12 19:15:43: --- Kernel modules from this package
[...]
@end smallexample
2012-07-06 17:23:57: --- Downloading all files
2012-07-06 17:24:02: --- Buildroot compiler and filesystem
2012-07-06 17:24:02: Uncompressing buildroot
2012-07-06 17:24:02: Patching buildroot
2012-07-06 17:24:02: Reconfiguring buildroot
2012-07-06 17:24:04: Compiling buildroot
2012-07-06 17:48:46: --- AT91Boot
2012-07-06 17:48:46: Patching AT91Boot
2012-07-06 17:48:46: Building AT91Boot
2012-07-06 17:48:50: --- Barebox
2012-07-06 17:48:50: Patching Barebox
2012-07-06 17:48:50: Building Barebox
2012-07-06 17:48:59: --- Linux kernel for switch
2012-07-06 17:50:32: --- Kernel modules from this package
2012-07-06 17:50:35: --- PTP daemon (noposix repository as a submodule)
2012-07-06 17:50:38: --- User space tools
2012-07-06 17:50:39: --- Deploying FPGA firmware
2012-07-06 17:50:39: --- Wrapping filesystem
2012-07-06 17:50:53: Complete build succeeded, apparently
@endsmallexample
You may prefer to save @i{stderr} with @i{stdout} to the log file
but still see the time-stamped messages from the scripts. In this
......
kernel/wbgen-regs/Makefile
View file @ b81a5d0e
# This Makefile is used to reproduce the headers from svn checkout.
# You need to have "wbgen2" in your command search path and the white-rabbit
# svn checkout in $SVN. Since this is only meant to be used by me,
# no serious checking is done
# List of input files in SVN checkout
MODULES = $(SVN)/trunk/hdl/modules
SPECS = $(SVN)/trunk/documentation/specifications
WB_ENDPOINT = $(MODULES)/wrsw_endpoint/ep_wishbone_controller.wb
WB_PPSG = $(MODULES)/wrsw_pps_gen/wrsw_pps_gen.wb
WB_CALIB = $(MODULES)/wrsw_calibrator_dmtd/wrsw_calibrator_dmtd.wb
WB_TSTAMP = $(MODULES)/wrsw_txtsu/wrsw_txtsu.wb
WB_RTU = $(MODULES)/wrsw_rtu/wrsw_rtu_wb.wb
WB_NIC = $(SPECS)/hdlspec/WRSW_wbc_internal_NIC/wr_nic.wb
HEADERS = endpoint-regs.h ppsg-regs.h calib-regs.h tstamp-regs.h rtu-regs.h \
nic-regs.h
# repos (wr-cores and wr-switch-hdl) Git checkout in $REPOS.
# Since this is only meant to be used by me (or Tom) no serious checking is done.
# List of input files in Git checkout
MODULES_WRS ?= $(REPOS)/wr-switch-hdl/modules
MODULES_WRC ?= $(REPOS)/wr-cores/modules
#SPECS = $(HW_REPO)/trunk/documentation/specifications
WB_ENDPOINT = $(MODULES_WRC)/wr_endpoint/ep_wishbone_controller.wb
WB_MDIO = $(MODULES_WRC)/wr_endpoint/pcs_regs.wb
WB_PPSG = $(MODULES_WRC)/wr_pps_gen/pps_gen_wb.wb
WB_TSTAMP = $(MODULES_WRS)/wrsw_txtsu/wrsw_txtsu.wb
WB_RTU = $(MODULES_WRS)/wrsw_rtu/rtu_wishbone_slave.wb
WB_NIC = $(MODULES_WRS)/wrsw_nic/wr_nic.wb
WB_SOFTPLL = $(MODULES_WRC)/wr_softpll_ng/spll_wb_slave.wb
HEADERS = endpoint-regs.h endpoint-mdio.h ppsg-regs.h tstamp-regs.h rtu-regs.h \
nic-regs.h softpll-regs.h
WBINPUT = $(HEADERS:.h=wb)
# No default, for people who types "make" everywhere (like me)
......@@ -28,7 +32,7 @@ headers: $(HEADERS)
%.h: %.wb
wbgen2 --cstyle=struct --co=$@ $<
sed -i 's,inttypes.h,linux/types.h,' $@
sed -i 's,#include <inttypes.h>,#ifdef __KERNEL__\n#include <linux/types.h>\n#else\n#include <stdint.h>\n#endif\n,' $@
sed -i '/ Created *: .*20[0-9][0-9]$$/ d' $@
sed -i 's/-REGS_WB//' $@
......@@ -37,9 +41,10 @@ headers: $(HEADERS)
# Do it silent so errors stand out
wbinput:
@cp $(WB_ENDPOINT) endpoint-regs.wb
@cp $(WB_MDIO) endpoint-mdio.wb
@cp $(WB_PPSG) ppsg-regs.wb
@cp $(WB_CALIB) calib-regs.wb
@cp $(WB_TSTAMP) tstamp-regs.wb
@cp $(WB_RTU) rtu-regs.wb
@cp $(WB_NIC) nic-regs.wb
@cp $(WB_SOFTPLL) softpll-regs.wb
@echo "Copied input files from subversions to local directory"
kernel/wbgen-regs/calib-regs.h deleted 100644 → 0
View file @ b1f76342
/*
Register definitions for slave core: DMTD PHY Calibrator
* File : calib-regs.h
* Author : auto-generated by wbgen2 from calib-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE calib-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CALIB
#define __WBGEN2_REGDEFS_CALIB
#include <linux/types.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Enable in reg: Control Register */
#define DPC_CR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Compare clock select in reg: Control Register */
#define DPC_CR_IN_SEL_MASK WBGEN2_GEN_MASK(8, 4)
#define DPC_CR_IN_SEL_SHIFT 8
#define DPC_CR_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define DPC_CR_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for field: DMTD averaging samples in reg: Control Register */
#define DPC_CR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define DPC_CR_N_AVG_SHIFT 16
#define DPC_CR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define DPC_CR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Status register */
/* definitions for field: Phase shift value in reg: Status register */
#define DPC_SR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DPC_SR_PS_VAL_SHIFT 0
#define DPC_SR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DPC_SR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase shift value ready in reg: Status register */
#define DPC_SR_PS_RDY WBGEN2_GEN_MASK(24, 1)
PACKED struct DPC_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Status register */
uint32_t SR;
};
#endif
kernel/wbgen-regs/calib-regs.wb deleted 100644 → 0
View file @ b1f76342
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "DMTD PHY Calibrator";
prefix = "dpc";
hdl_entity = "dmtd_calibrator_wb";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Enable";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Compare clock select";
prefix = "IN_SEL";
type = SLV;
size = 4;
align = 8;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Status register";
prefix = "SR";
field {
name = "Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
};
userspace/include/hw/endpoint_mdio.h → kernel/wbgen-regs/endpoint-mdio.h
View file @ b81a5d0e
/*
Register definitions for slave core: WR Endpoint 1000base-X TBI PCS register block
* File : ../../../software/include/hw/endpoint_mdio.h
* Author : auto-generated by wbgen2 from pcs_regs.wb
* Created : Sun Apr 10 01:27:44 2011
* File : endpoint-mdio.h
* Author : auto-generated by wbgen2 from endpoint-mdio.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE endpoint-mdio.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_PCS_REGS_WB
#define __WBGEN2_REGDEFS_PCS_REGS_WB
#ifndef __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
#define __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -362,26 +366,32 @@
#define MDIO_WR_SPEC_CAL_CRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: GTP RX Bitslide in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_BSLIDE_MASK WBGEN2_GEN_MASK(4, 4)
#define MDIO_WR_SPEC_BSLIDE_MASK WBGEN2_GEN_MASK(4, 5)
#define MDIO_WR_SPEC_BSLIDE_SHIFT 4
#define MDIO_WR_SPEC_BSLIDE_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define MDIO_WR_SPEC_BSLIDE_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* [0x0]: REG MDIO Control Register */
#define MDIO_REG_MCR 0x00000000
/* [0x4]: REG MDIO Status Register */
#define MDIO_REG_MSR 0x00000004
/* [0x8]: REG MDIO PHY Identification Register 1 */
#define MDIO_REG_PHYSID1 0x00000008
/* [0xc]: REG MDIO PHY Identification Register 2 */
#define MDIO_REG_PHYSID2 0x0000000c
/* [0x10]: REG MDIO Auto-Negotiation Advertisement Register */
#define MDIO_REG_ADVERTISE 0x00000010
/* [0x14]: REG MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_REG_LPA 0x00000014
/* [0x18]: REG MDIO Auto-Negotiation Expansion Register */
#define MDIO_REG_EXPANSION 0x00000018
/* [0x3c]: REG MDIO Extended Status Register */
#define MDIO_REG_ESTATUS 0x0000003c
/* [0x40]: REG WhiteRabbit-specific Configuration Register */
#define MDIO_REG_WR_SPEC 0x00000040
#define MDIO_WR_SPEC_BSLIDE_W(value) WBGEN2_GEN_WRITE(value, 4, 5)
#define MDIO_WR_SPEC_BSLIDE_R(reg) WBGEN2_GEN_READ(reg, 4, 5)
PACKED struct MDIO_WB {
/* [0x0]: REG MDIO Control Register */
uint32_t MCR;
/* [0x4]: REG MDIO Status Register */
uint32_t MSR;
/* [0x8]: REG MDIO PHY Identification Register 1 */
uint32_t PHYSID1;
/* [0xc]: REG MDIO PHY Identification Register 2 */
uint32_t PHYSID2;
/* [0x10]: REG MDIO Auto-Negotiation Advertisement Register */
uint32_t ADVERTISE;
/* [0x14]: REG MDIO Auto-Negotiation Link Partner Ability Register */
uint32_t LPA;
/* [0x18]: REG MDIO Auto-Negotiation Expansion Register */
uint32_t EXPANSION;
/* padding to: 15 words */
uint32_t __padding_0[8];
/* [0x3c]: REG MDIO Extended Status Register */
uint32_t ESTATUS;
/* [0x40]: REG WhiteRabbit-specific Configuration Register */
uint32_t WR_SPEC;
};
#endif
kernel/wbgen-regs/endpoint-mdio.wb 0 → 100644
View file @ b81a5d0e
This diff is collapsed.
kernel/wbgen-regs/endpoint-regs.h
View file @ b81a5d0e
......@@ -13,7 +13,12 @@
#ifndef __WBGEN2_REGDEFS_ENDPOINT
#define __WBGEN2_REGDEFS_ENDPOINT
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -265,6 +270,7 @@
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BASE 0x00000080 /* base address */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
......
kernel/wbgen-regs/nic-regs.h
View file @ b81a5d0e
......@@ -13,7 +13,12 @@
#ifndef __WBGEN2_REGDEFS_NIC
#define __WBGEN2_REGDEFS_NIC
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -76,7 +81,7 @@
#define NIC_TX1_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX1_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 1 register 2 */
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 1 register 2 */
#define NIC_TX1_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX1_D2_LEN_SHIFT 16
#define NIC_TX1_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -118,7 +123,7 @@
#define NIC_TX2_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX2_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 2 register 2 */
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D2_LEN_SHIFT 16
#define NIC_TX2_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -160,7 +165,7 @@
#define NIC_TX3_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX3_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 3 register 2 */
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D2_LEN_SHIFT 16
#define NIC_TX3_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -202,7 +207,7 @@
#define NIC_TX4_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX4_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 4 register 2 */
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D2_LEN_SHIFT 16
#define NIC_TX4_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -244,7 +249,7 @@
#define NIC_TX5_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX5_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 5 register 2 */
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D2_LEN_SHIFT 16
#define NIC_TX5_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -286,7 +291,7 @@
#define NIC_TX6_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX6_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 6 register 2 */
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D2_LEN_SHIFT 16
#define NIC_TX6_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -328,7 +333,7 @@
#define NIC_TX7_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX7_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 7 register 2 */
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D2_LEN_SHIFT 16
#define NIC_TX7_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -370,7 +375,7 @@
#define NIC_TX8_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX8_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 8 register 2 */
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D2_LEN_SHIFT 16
#define NIC_TX8_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
......@@ -401,6 +406,9 @@
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 1 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 1 register 2 */
......@@ -446,6 +454,9 @@
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 2 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 2 register 2 */
......@@ -491,6 +502,9 @@
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 3 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 3 register 2 */
......@@ -536,6 +550,9 @@
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 4 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 4 register 2 */
......@@ -581,6 +598,9 @@
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 5 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 5 register 2 */
......@@ -626,6 +646,9 @@
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 6 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 6 register 2 */
......@@ -671,6 +694,9 @@
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 7 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 7 register 2 */
......@@ -716,6 +742,9 @@
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 8 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 8 register 2 */
......@@ -800,6 +829,7 @@
/* definitions for field: Transmit Error in reg: Interrupt status register */
#define NIC_EIC_ISR_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for RAM: TX/RX Buffers */
#define NIC_MEM_BASE 0x00008000 /* base address */
#define NIC_MEM_BYTES 0x00008000 /* size in bytes */
#define NIC_MEM_WORDS 0x00002000 /* size in 32-bit words, 32-bit aligned */
......
kernel/wbgen-regs/nic-regs.wb
View file @ b81a5d0e
......@@ -75,10 +75,10 @@ top = peripheral {
field {
name = "Buffer Not Available";
prefix = "bna";
description = "No buffers were available when receiving a packet. Cleared by writing a one to this bit";
description = "No buffers were available when receiving a packet.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
};
......@@ -138,31 +138,30 @@ top = peripheral {
-- prefix = "dtx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- ram {
-- name = "RX descriptors mem";
-- ram {
-- name = "RX descriptors mem";
-- prefix = "drx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
ram {
name = "TX/RX Buffers";
prefix = "mem";
-- 8192 * 32 = 32Kb
size = 8192;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
ram {
name = "TX/RX Buffers";
prefix = "mem";
-- 8192 * 32 = 32Kb
size = 8192;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
......@@ -235,7 +234,6 @@ TX_desc_template =
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
-- extended the sizes to 16 bits (although the buffer is 32kB-long)
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
......@@ -246,7 +244,7 @@ TX_desc_template =
};
field {
name = "Length of buffer in bytes";
name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
prefix = "len";
type = SLV;
size = 16;
......@@ -319,6 +317,18 @@ RX_desc_template = {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX Timestamp (possibly) incorrect";
prefix = "TS_INCORRECT";
align = 15;
description = "1 - there is a risk that the timestamp in RX_D2 is invalid, because it was taken during counter adjustment,\
0 - RX timestamp OK.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -329,8 +339,8 @@ RX_desc_template = {
field {
name = "RX_TS_R";
description = "Value of the RX timestamp (rising edge bits)";
prefix = "TS_R";
description = "Value of the RX timestamp (rising edge bits)";
size = 28;
type = SLV;
access_bus = READ_ONLY;
......
kernel/wbgen-regs/ppsg-regs.h
View file @ b81a5d0e
......@@ -13,7 +13,12 @@
#ifndef __WBGEN2_REGDEFS_PPSG
#define __WBGEN2_REGDEFS_PPSG
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -62,6 +67,17 @@
/* definitions for register: UTC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
......@@ -77,6 +93,8 @@ PACKED struct PPSG_WB {
uint32_t ADJ_UTCLO;
/* [0x18]: REG UTC Adjustment register (most-significant part) */
uint32_t ADJ_UTCHI;
/* [0x1c]: REG External sync control register */
uint32_t ESCR;
};
#endif
kernel/wbgen-regs/ppsg-regs.wb
View file @ b81a5d0e
......@@ -56,6 +56,7 @@ peripheral {
clock = "refclk_i";
};
field {
name = "PPS Pulse width";
description = "Width of generated PPS pulses in 125 MHz refernce clock cycles";
......@@ -151,6 +152,46 @@ peripheral {
};
};
reg {
name = "External sync control register";
prefix = "ESCR";
field {
name = "Sync to external PPS input";
description = "write 1: Waits until a pulse on external PPS input arrives and re-synchronizes the PPS counter to it\
write 0: no effect\
read 1: external synchronization done\
read 0: external synchronization in progress";
type = BIT;
prefix = "SYNC";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "PPS output valid";
description = "write 1: PPS output provides reliable 1-PPS signal\
write 0: PPS output is invalid";
prefix = "PPS_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Timecode output(UTC+cycles) valid";
description = "write 1: Timecode output provides valid time\
write 0: Timecode output does not provide valid time";
prefix = "TM_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
};
};
kernel/wbgen-regs/rtu-regs.h
View file @ b81a5d0e
......@@ -13,7 +13,12 @@
#ifndef __WBGEN2_REGDEFS_RTU
#define __WBGEN2_REGDEFS_RTU
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......
kernel/wbgen-regs/softpll-regs.h 0 → 100644
View file @ b81a5d0e
This diff is collapsed.
kernel/wbgen-regs/softpll-regs.wb 0 → 100644
View file @ b81a5d0e
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Softcore PLL";
hdl_entity = "spll_wb_slave";
prefix = "spll";
reg {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Period detector reference select";
prefix = "PER_SEL";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
align = 8;
name = "Number of reference channels (max: 32)";
prefix = "N_REF";
type = SLV;
size = 6;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 8;
name = "Number of output channels (max: 8)";
prefix = "N_OUT";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Enable Period Measurement";
prefix = "PER_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
---------------------------------------------
-- External clock input
---------------------------------------------
reg {
name = "External Clock Control Register";
prefix = "ECCR";
field {
name = "Enable External Clock BB Detector";
prefix = "EXT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
0: no support for external 10 MHz clock input.";
prefix = "EXT_SUPPORTED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
0: reference input dead";
prefix = "EXT_REF_PRESENT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
field {
name = "DMTD Clock Undersampling Divider";
prefix = "GATE_DIV";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reference Channel Undersampling Enable Register";
prefix = "RCGER";
field {
name = "Reference Channel Undersampling Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
};
};
reg {
name = "Output Channel Control Register";
prefix = "OCCR";
field {
align = 8;
name = "Output Channel HW enable flag";
prefix = "OUT_EN";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Output Channel locked flag";
prefix = "OUT_LOCK";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reference Channel Enable Register";
prefix = "RCER";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Output Channel Enable Register";
prefix = "OCER";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "HPLL Period Error";
prefix = "PER_HPLL";
field {
name = "Period error value";
prefix = "ERROR";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
field {
name = "Period Error Valid";
prefix = "VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Helper DAC Output";
prefix = "DAC_HPLL";
field {
name = "DAC value";
type = PASS_THROUGH;
size = 16;
};
};
reg {
name = "Main DAC Output";
prefix = "DAC_MAIN";
field {
name = "DAC value";
prefix = "VALUE";
type = PASS_THROUGH;
size = 16;
};
field {
name = "DAC select";
prefix = "DAC_SEL";
description = "Selects the output DAC to be updated with VALUE";
type = PASS_THROUGH;
size = 4;
};
};
reg {
name = "Deglitcher threshold";
prefix = "DEGLITCH_THR";
field {
name = "Threshold";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Debug FIFO Register - SPLL side";
prefix = "DFR_SPLL";
field {
name = "Debug Value";
prefix = "VALUE";
size = 31;
type = PASS_THROUGH;
};
field {
name = "End-of-Sample";
prefix = "EOS";
size = 1;
type = PASS_THROUGH;
};
};
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
size = 8192;
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
field {
name = "Value";
prefix = "VALUE";
type = SLV;
size = 32;
};
field {
name = "Seq ID";
prefix = "SEQ_ID";
type = SLV;
size = 16;
};
};
fifo_reg {
name = "Tag Readout Register";
prefix = "TRR";
direction = CORE_TO_BUS;
size = 32;
flags_dev = {FIFO_FULL, FIFO_EMPTY};
flags_bus = {FIFO_EMPTY};
field {
name = "Tag value";
prefix = "VALUE";
type = SLV;
size = 24;
};
field {
name = "Channel ID";
description = "Tagged Channel ID: 0-31: reference tags, 32-47: output tags";
prefix = "CHAN_ID";
type = SLV;
size = 7;
};
field {
name = "Discontinuous bit";
prefix = "DISC";
description = "1: previous tag has been dropped due to FIFO overflow";
type = BIT;
};
};
irq {
name = "Got a tag";
prefix = "TAG";
trigger = LEVEL_1;
};
};
kernel/wbgen-regs/tstamp-regs.h
View file @ b81a5d0e
......@@ -13,7 +13,12 @@
#ifndef __WBGEN2_REGDEFS_TSTAMP
#define __WBGEN2_REGDEFS_TSTAMP
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -78,6 +83,11 @@
#define TXTSU_TSF_R1_FID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define TXTSU_TSF_R1_FID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 2 */
/* definitions for field: Timestamp (possibly) incorrect in reg: FIFO 'Timestamp FIFO' data output register 2 */
#define TXTSU_TSF_R2_INCORRECT WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Timestamp FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO' control/status register */
......@@ -105,7 +115,9 @@ PACKED struct TXTSU_WB {
uint32_t TSF_R0;
/* [0x14]: REG FIFO 'Timestamp FIFO' data output register 1 */
uint32_t TSF_R1;
/* [0x18]: REG FIFO 'Timestamp FIFO' control/status register */
/* [0x18]: REG FIFO 'Timestamp FIFO' data output register 2 */
uint32_t TSF_R2;
/* [0x1c]: REG FIFO 'Timestamp FIFO' control/status register */
uint32_t TSF_CSR;
};
......
kernel/wbgen-regs/tstamp-regs.wb
View file @ b81a5d0e
......@@ -19,7 +19,8 @@ peripheral {
properly (there was no metastability/setup/hold violation)\
Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
- FID - Frame identifier assigned by the NIC\
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames";
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames;\
- INCORRECT - timestamp may be incorrect, it has been generated during timebase adjustment";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
......@@ -58,15 +59,23 @@ peripheral {
type = SLV;
size = 16;
align = 16;
};
};
};
field {
name = "Timestamp (possibly) incorrect";
description = "1: This timestamp may be incorrect (generated during PPS adjustment)\
0: Timestamp is correct.";
prefix = "incorrect";
type = BIT;
};
};
-- TXTSU interrupts
irq {
name = "TXTSU fifo not-empty";
description = "Interrupt active when TXTSU shared FIFO contains any timestamps.";
prefix = "nempty";
trigger = LEVEL_0;
trigger = LEVEL_1;
};
};
\ No newline at end of file
kernel/wr_nic/nic-core.c
View file @ b81a5d0e
......@@ -352,8 +352,6 @@ static void __wrn_rx_descriptor(struct wrn_dev *wrn, int desc)
/* RX timestamping part */
hwts = skb_hwtstamps(skb);
wrn_ppsg_read_time(wrn, &counter_ppsg, &utc);
if(counter_ppsg < REFCLK_FREQ/4 && ts_r > 3*REFCLK_FREQ/4)
......@@ -371,7 +369,13 @@ static void __wrn_rx_descriptor(struct wrn_dev *wrn, int desc)
ts.tv_nsec & 0x7fffffff,
ts.tv_sec & 0x80000000 ? 1 :0);
hwts->hwtstamp = timespec_to_ktime(ts);
/* If the timestamp was reported as incorrect, pass 0 instead */
if (! (r1 & NIC_RX1_D1_TS_INCORRECT)) /* FIXME: bit name possibly? */
{
hwts = skb_hwtstamps(skb);
hwts->hwtstamp = timespec_to_ktime(ts);
}
skb->protocol = eth_type_trans(skb, dev);
skb->ip_summed = CHECKSUM_UNNECESSARY;
dev->last_rx = jiffies;
......
kernel/wr_nic/nic-hardware.h
View file @ b81a5d0e
......@@ -79,7 +79,6 @@ enum fpga_blocks {
*/
#include "../wbgen-regs/endpoint-regs.h"
#include "../wbgen-regs/ppsg-regs.h"
#include "../wbgen-regs/calib-regs.h"
#include "../wbgen-regs/nic-regs.h"
#include "../wbgen-regs/tstamp-regs.h"
......
kernel/wr_nic/timestamp.c
View file @ b81a5d0e
/*
/*\
* Timestamping routines for WR Switch
*
* Copyright (C) 2010 CERN (www.cern.ch)
......@@ -37,15 +37,22 @@ void wrn_tstamp_find_skb(struct wrn_dev *wrn, int desc)
pr_debug("%s: found\n", __func__);
/* so we found the skb, do the timestamping magic */
hwts = skb_hwtstamps(skb);
wrn_ppsg_read_time(wrn, &counter_ppsg, &utc);
if(counter_ppsg < wrn->ts_buf[i].ts)
/* The timestamp nanoseconds value is closer to the end of previous second, but the UTC time
read from PPSG is at the beginning of the next second: adjust UTC seconds to avoid 1 sec
"jump" */
if(counter_ppsg < REFCLK_FREQ/4 && wrn->ts_buf[i].ts > 3*REFCLK_FREQ/4)
utc--;
ts.tv_sec = (s32)utc & 0x7fffffff;
ts.tv_nsec = wrn->ts_buf[i].ts * NSEC_PER_TICK;
hwts->hwtstamp = timespec_to_ktime(ts);
skb_tstamp_tx(skb, hwts);
if (! (wrn->ts_buf[i].valid & TS_INVALID))
{
hwts = skb_hwtstamps(skb);
hwts->hwtstamp = timespec_to_ktime(ts);
skb_tstamp_tx(skb, hwts);
}
dev_kfree_skb_irq(skb);
/* release both the descriptor and the tstamp entry */
......@@ -54,10 +61,11 @@ void wrn_tstamp_find_skb(struct wrn_dev *wrn, int desc)
}
/* This function records the timestamp in a list -- called from interrupt */
static int record_tstamp(struct wrn_dev *wrn, u32 tsval, u32 idreg)
static int record_tstamp(struct wrn_dev *wrn, u32 tsval, u32 idreg, u32 r2)
{
int port_id = TXTSU_TSF_R1_PID_R(idreg);
int frame_id = TXTSU_TSF_R1_FID_R(idreg);
int ts_incorrect = r2 & TXTSU_TSF_R2_INCORRECT;
struct skb_shared_hwtstamps *hwts;
struct timespec ts;
struct sk_buff *skb;
......@@ -75,7 +83,6 @@ static int record_tstamp(struct wrn_dev *wrn, u32 tsval, u32 idreg)
if (i < WRN_NR_DESC) {
/*printk("%s: found\n", __func__);*/
skb = wrn->skb_desc[i].skb;
hwts = skb_hwtstamps(skb);
wrn_ppsg_read_time(wrn, &counter_ppsg, &utc);
if(counter_ppsg < (tsval & 0xfffffff))
......@@ -83,13 +90,19 @@ static int record_tstamp(struct wrn_dev *wrn, u32 tsval, u32 idreg)
ts.tv_sec = (s32)utc & 0x7fffffff;
ts.tv_nsec = (tsval & 0xfffffff) * NSEC_PER_TICK;
hwts->hwtstamp = timespec_to_ktime(ts);
skb_tstamp_tx(skb, hwts);
/* Provide the timestamp for the userland only if we're 100% sure about its correctness */
if (!ts_incorrect)
{
hwts = skb_hwtstamps(skb);
hwts->hwtstamp = timespec_to_ktime(ts);
skb_tstamp_tx(skb, hwts);
}
dev_kfree_skb_irq(skb);
wrn->skb_desc[i].skb = 0;
return 0;
}
/* Otherwise, save it to the list */
/* Otherwise, save it to the list, in an empty slot */
for(i = 0; i < WRN_TS_BUF_SIZE; i++)
if(!wrn->ts_buf[i].valid)
break;
......@@ -102,7 +115,9 @@ static int record_tstamp(struct wrn_dev *wrn, u32 tsval, u32 idreg)
wrn->ts_buf[i].ts = tsval;
wrn->ts_buf[i].port_id = port_id;
wrn->ts_buf[i].frame_id = frame_id;
wrn->ts_buf[i].valid = 1;
wrn->ts_buf[i].valid = TS_PRESENT;
if (ts_incorrect)
wrn->ts_buf[i].valid |= TS_INVALID;
return 0;
}
......@@ -110,14 +125,15 @@ irqreturn_t wrn_tstamp_interrupt(int irq, void *dev_id)
{
struct wrn_dev *wrn = dev_id;
struct TXTSU_WB *regs = wrn->txtsu_regs;
u32 r0, r1;
u32 r0, r1, r2;
/* printk("%s: %i\n", __func__, __LINE__); */
/* FIXME: locking */
r0 = readl(&regs->TSF_R0);
r1 = readl(&regs->TSF_R1);
r2 = readl(&regs->TSF_R2);
if(record_tstamp(wrn, r0, r1) < 0) {
if(record_tstamp(wrn, r0, r1, r2) < 0) {
printk("%s: ENOMEM in the TS buffer. Disabling TX stamping.\n",
__func__);
writel(TXTSU_EIC_IER_NEMPTY, &wrn->txtsu_regs->EIC_IDR);
......
kernel/wr_nic/wr-nic.h
View file @ b81a5d0e
......@@ -53,6 +53,9 @@ struct wrn_tx_tstamp {
u16 frame_id;
u32 ts;
};
/* bits for "valid" field */
#define TS_PRESENT 1
#define TS_INVALID 2 /* as reported by hw: we return 0 as timestamp */
/* We must remember both skb and id for each pending descriptor */
struct wrn_desc_pending {
......
kernel/wr_vic/endpoint_mdio.h deleted 100644 → 0
View file @ b1f76342
This diff is collapsed.
kernel/wr_vic/endpoint_regs.h deleted 100644 → 0
View file @ b1f76342
/*
Register definitions for slave core: WR switch endpoint controller
* File : ../../../software/include/hw/endpoint_regs.h
* Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
* Created : Wed Nov 3 19:00:12 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#define __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Endpoint Control Register */
/* definitions for field: Port identifier in reg: Endpoint Control Register */
#define EP_ECR_PORTID_MASK WBGEN2_GEN_MASK(0, 5)
#define EP_ECR_PORTID_SHIFT 0
#define EP_ECR_PORTID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define EP_ECR_PORTID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reset event counters in reg: Endpoint Control Register */
#define EP_ECR_RST_CNT WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Transmit framer enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN_FRA WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Receive deframer enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN_FRA WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Timestamping Control Register */
/* definitions for field: Transmit timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_TXTS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Receive timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_RXTS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamping counter synchronization start in reg: Timestamping Control Register */
#define EP_TSCR_CS_START WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Timestamping counter synchronization done in reg: Timestamping Control Register */
#define EP_TSCR_CS_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: RX Deframer Control Register */
/* definitions for field: RX accept runts in reg: RX Deframer Control Register */
#define EP_RFCR_A_RUNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX accept giants in reg: RX Deframer Control Register */
#define EP_RFCR_A_GIANT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RX accept HP in reg: RX Deframer Control Register */
#define EP_RFCR_A_HP WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX accept fragments in reg: RX Deframer Control Register */
#define EP_RFCR_A_FRAG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX 802.1q port mode in reg: RX Deframer Control Register */
#define EP_RFCR_QMODE_MASK WBGEN2_GEN_MASK(4, 2)
#define EP_RFCR_QMODE_SHIFT 4
#define EP_RFCR_QMODE_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define EP_RFCR_QMODE_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Force 802.1q priority in reg: RX Deframer Control Register */
#define EP_RFCR_FIX_PRIO WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port-assigned 802.1x priority in reg: RX Deframer Control Register */
#define EP_RFCR_PRIO_VAL_MASK WBGEN2_GEN_MASK(8, 3)
#define EP_RFCR_PRIO_VAL_SHIFT 8
#define EP_RFCR_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define EP_RFCR_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Port-assigned VID in reg: RX Deframer Control Register */
#define EP_RFCR_VID_VAL_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_RFCR_VID_VAL_SHIFT 16
#define EP_RFCR_VID_VAL_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_RFCR_VID_VAL_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Flow Control Register */
/* definitions for field: RX Pause enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX Pause enable in reg: Flow Control Register */
#define EP_FCR_TXPAUSE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX pause threshold in reg: Flow Control Register */
#define EP_FCR_TX_THR_MASK WBGEN2_GEN_MASK(8, 8)
#define EP_FCR_TX_THR_SHIFT 8
#define EP_FCR_TX_THR_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define EP_FCR_TX_THR_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: TX pause quanta in reg: Flow Control Register */
#define EP_FCR_TX_QUANTA_MASK WBGEN2_GEN_MASK(16, 16)
#define EP_FCR_TX_QUANTA_SHIFT 16
#define EP_FCR_TX_QUANTA_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define EP_FCR_TX_QUANTA_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Endpoint MAC address high part register */
/* definitions for register: Endpoint MAC address low part register */
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for register: MDIO Control Register */
/* definitions for field: MDIO Register Value in reg: MDIO Control Register */
#define EP_MDIO_CR_DATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_CR_DATA_SHIFT 0
#define EP_MDIO_CR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_CR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Register Address in reg: MDIO Control Register */
#define EP_MDIO_CR_ADDR_MASK WBGEN2_GEN_MASK(16, 8)
#define EP_MDIO_CR_ADDR_SHIFT 16
#define EP_MDIO_CR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define EP_MDIO_CR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: MDIO Read/Write select in reg: MDIO Control Register */
#define EP_MDIO_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: MDIO Status Register */
/* definitions for field: MDIO Read Value in reg: MDIO Status Register */
#define EP_MDIO_SR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_SR_RDATA_SHIFT 0
#define EP_MDIO_SR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_SR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Ready in reg: MDIO Status Register */
#define EP_MDIO_SR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
/* [0x0]: REG Endpoint Control Register */
#define EP_REG_ECR 0x00000000
/* [0x4]: REG Timestamping Control Register */
#define EP_REG_TSCR 0x00000004
/* [0x8]: REG RX Deframer Control Register */
#define EP_REG_RFCR 0x00000008
/* [0xc]: REG Flow Control Register */
#define EP_REG_FCR 0x0000000c
/* [0x10]: REG Endpoint MAC address high part register */
#define EP_REG_MACH 0x00000010
/* [0x14]: REG Endpoint MAC address low part register */
#define EP_REG_MACL 0x00000014
/* [0x18]: REG DMTD Control Register */
#define EP_REG_DMCR 0x00000018
/* [0x1c]: REG DMTD Status register */
#define EP_REG_DMSR 0x0000001c
/* [0x20]: REG MDIO Control Register */
#define EP_REG_MDIO_CR 0x00000020
/* [0x24]: REG MDIO Status Register */
#define EP_REG_MDIO_SR 0x00000024
#define EP_REG_IDCODE 0x00000028
/* definitions for register: WhiteRabbit-specific Configuration Register */
/* definitions for field: TX Calibration Pattern in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_TX_CAL WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Calibration Pattern RX Status in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_RX_CAL_STAT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reset calibration counter in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_CAL_CRST WBGEN2_GEN_MASK(2, 1)
/* [0x10]: REG WhiteRabbit-specific Configuration Register */
#define MDIO_REG_WR_SPEC 0x00000010
#endif
kernel/wr_vic/minic_regs.h deleted 100644 → 0
View file @ b1f76342
/*
Register definitions for slave core: Mini NIC for WhiteRabbit
* File : ../../../software/include/hw/minic_regs.h
* Author : auto-generated by wbgen2 from mini_nic.wb
* Created : Fri Jul 30 00:33:27 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_MINI_NIC_WB
#define __WBGEN2_REGDEFS_MINI_NIC_WB
//#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: miNIC Control Register */
/* definitions for field: TX DMA start in reg: miNIC Control Register */
#define MINIC_MCR_TX_START WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX DMA idle in reg: miNIC Control Register */
#define MINIC_MCR_TX_IDLE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_TX_ERROR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX DMA ready in reg: miNIC Control Register */
#define MINIC_MCR_RX_READY WBGEN2_GEN_MASK(8, 1)
/* definitions for field: RX DMA buffer full in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL WBGEN2_GEN_MASK(9, 1)
/* definitions for field: RX DMA enable in reg: miNIC Control Register */
#define MINIC_MCR_RX_EN WBGEN2_GEN_MASK(10, 1)
/* definitions for register: TX DMA Address */
/* definitions for register: RX DMA Address */
/* definitions for register: RX buffer size register */
/* definitions for register: Interrupt disable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt enable register */
#define MINIC_EIC_IER_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: TX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: TX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt status register */
#define MINIC_EIC_ISR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 0 */
/* definitions for field: Timestamp value in reg: FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_TSFIFO_R0_TSVAL_MASK WBGEN2_GEN_MASK(0, 32)
#define MINIC_TSFIFO_R0_TSVAL_SHIFT 0
#define MINIC_TSFIFO_R0_TSVAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MINIC_TSFIFO_R0_TSVAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 1 */
/* definitions for field: Port ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_PID_MASK WBGEN2_GEN_MASK(0, 5)
#define MINIC_TSFIFO_R1_PID_SHIFT 0
#define MINIC_TSFIFO_R1_PID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MINIC_TSFIFO_R1_PID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Frame ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_FID_MASK WBGEN2_GEN_MASK(5, 16)
#define MINIC_TSFIFO_R1_FID_SHIFT 5
#define MINIC_TSFIFO_R1_FID_W(value) WBGEN2_GEN_WRITE(value, 5, 16)
#define MINIC_TSFIFO_R1_FID_R(reg) WBGEN2_GEN_READ(reg, 5, 16)
/* definitions for register: FIFO 'TX timestamp FIFO' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_TSFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG miNIC Control Register */
#define MINIC_REG_MCR 0x00000000
/* [0x4]: REG TX DMA Address */
#define MINIC_REG_TX_ADDR 0x00000004
/* [0x8]: REG RX DMA Address */
#define MINIC_REG_RX_ADDR 0x00000008
/* [0xc]: REG RX buffer size register */
#define MINIC_REG_RX_AVAIL 0x0000000c
/* [0x20]: REG Interrupt disable register */
#define MINIC_REG_EIC_IDR 0x00000020
/* [0x24]: REG Interrupt enable register */
#define MINIC_REG_EIC_IER 0x00000024
/* [0x28]: REG Interrupt mask register */
#define MINIC_REG_EIC_IMR 0x00000028
/* [0x2c]: REG Interrupt status register */
#define MINIC_REG_EIC_ISR 0x0000002c
/* [0x30]: REG FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_REG_TSFIFO_R0 0x00000030
/* [0x34]: REG FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_REG_TSFIFO_R1 0x00000034
/* [0x38]: REG FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_REG_TSFIFO_CSR 0x00000038
#define MINIC_PBUF_SIZE_LOG2 (12)
#define MINIC_PBUF_SIZE (1<<(MINIC_PBUF_SIZE_LOG2+2))
#define MINIC_BASE_IO 0x0
#define MINIC_BASE_PBUF (2<<(MINIC_PBUF_SIZE_LOG2+2))
#define MINIC_BASE_ENDPOINT (1<<(MINIC_PBUF_SIZE_LOG2+2))
#define MINIC_BASE_GIGASPY (3<<(MINIC_PBUF_SIZE_LOG2+2))
#endif
kernel/wr_vic/pps_gen_regs.h deleted 100644 → 0
View file @ b1f76342
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : ../../../software/include/hw/pps_gen_regs.h
* Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
* Created : Sat Sep 11 22:22:55 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Reset counter in reg: Control Register */
#define PPSG_CR_CNT_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable counter in reg: Control Register */
#define PPSG_CR_CNT_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Adjust offset in reg: Control Register */
#define PPSG_CR_CNT_ADJ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Set time in reg: Control Register */
#define PPSG_CR_CNT_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: PPS Pulse width in reg: Control Register */
#define PPSG_CR_PWIDTH_MASK WBGEN2_GEN_MASK(4, 28)
#define PPSG_CR_PWIDTH_SHIFT 4
#define PPSG_CR_PWIDTH_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define PPSG_CR_PWIDTH_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Nanosecond counter register */
/* definitions for register: UTC Counter register (least-significant part) */
/* definitions for register: UTC Counter register (most-significant part) */
/* definitions for register: Nanosecond adjustment register */
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
#define PPSG_REG_CNTR_NSEC 0x00000004
/* [0x8]: REG UTC Counter register (least-significant part) */
#define PPSG_REG_CNTR_UTCLO 0x00000008
/* [0xc]: REG UTC Counter register (most-significant part) */
#define PPSG_REG_CNTR_UTCHI 0x0000000c
/* [0x10]: REG Nanosecond adjustment register */
#define PPSG_REG_ADJ_NSEC 0x00000010
/* [0x14]: REG UTC Adjustment register (least-significant part) */
#define PPSG_REG_ADJ_UTCLO 0x00000014
/* [0x18]: REG UTC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_UTCHI 0x00000018
#endif
patches/buildroot/buildroot-config-wrswitch
View file @ b81a5d0e
#
# Automatically generated make config: don't edit
# Buildroot 2011.11 Configuration
# Sat Mar 10 09:22:01 2012
# Fri Jul 6 17:17:43 2012
#
BR2_HAVE_DOT_CONFIG=y
BR2_arm=y
......@@ -157,7 +157,7 @@ BR2_GCC_ENABLE_TLS=y
# Gdb Options
#
BR2_PACKAGE_GDB=y
# BR2_PACKAGE_GDB_SERVER is not set
BR2_PACKAGE_GDB_SERVER=y
# BR2_PACKAGE_GDB_HOST is not set
# BR2_GDB_VERSION_7_1 is not set
# BR2_GDB_VERSION_7_2 is not set
......@@ -195,7 +195,7 @@ BR2_PTHREADS_NATIVE=y
# System configuration
#
BR2_TARGET_GENERIC_HOSTNAME="wrs3"
BR2_TARGET_GENERIC_ISSUE="WR Switch V3"
BR2_TARGET_GENERIC_ISSUE="Welcome to WR Switch V3"
# BR2_ROOTFS_DEVICE_CREATION_STATIC is not set
# BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS is not set
BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV=y
......@@ -223,8 +223,8 @@ BR2_BUSYBOX_VERSION_1_19_X=y
# BR2_PACKAGE_BUSYBOX_SNAPSHOT is not set
BR2_BUSYBOX_VERSION="1.19.3"
BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox-1.19.x.config"
# BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set
# BR2_PACKAGE_CUSTOMIZE is not set
BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
BR2_PACKAGE_CUSTOMIZE=y
#
# Audio and video libraries and applications
......@@ -302,6 +302,7 @@ BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox-1.19.x.config"
# Compressors and decompressors
#
# BR2_PACKAGE_BZIP2 is not set
# BR2_PACKAGE_GZIP is not set
# BR2_PACKAGE_LZOP is not set
# BR2_PACKAGE_XZ is not set
......@@ -319,7 +320,7 @@ BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox-1.19.x.config"
#
# lmbench requires a toolchain with RPC support
#
# BR2_PACKAGE_LSOF is not set
BR2_PACKAGE_LSOF=y
# BR2_PACKAGE_LTP_TESTSUITE is not set
BR2_PACKAGE_LTRACE=y
# BR2_PACKAGE_MEMSTAT is not set
......@@ -341,9 +342,13 @@ BR2_PACKAGE_STRACE=y
# BR2_PACKAGE_BISON is not set
# BR2_PACKAGE_BSDIFF is not set
# BR2_PACKAGE_CCACHE is not set
# BR2_PACKAGE_COREUTILS is not set
# BR2_PACKAGE_CVS is not set
# BR2_PACKAGE_DIFFUTILS is not set
# BR2_PACKAGE_DISTCC is not set
# BR2_PACKAGE_FINDUTILS is not set
# BR2_PACKAGE_FLEX is not set
# BR2_PACKAGE_GAWK is not set
#
# gcc needs development files in target filesystem
......@@ -355,13 +360,17 @@ BR2_PACKAGE_STRACE=y
#
# gperf requires a toolchain with C++ support enabled
#
# BR2_PACKAGE_GREP is not set
# BR2_PACKAGE_MAKE is not set
# BR2_PACKAGE_MPC is not set
# BR2_PACKAGE_MPFR is not set
# BR2_PACKAGE_LIBTOOL is not set
# BR2_PACKAGE_M4 is not set
# BR2_PACKAGE_PATCH is not set
# BR2_PACKAGE_PKG_CONFIG is not set
# BR2_PACKAGE_SED is not set
# BR2_PACKAGE_SSTRIP is not set
# BR2_PACKAGE_TAR is not set
#
# Games
......@@ -384,6 +393,7 @@ BR2_PACKAGE_STRACE=y
# BR2_PACKAGE_DIRECTFB is not set
# BR2_PACKAGE_FBDUMP is not set
# BR2_PACKAGE_FBGRAB is not set
# BR2_PACKAGE_FBSET is not set
# BR2_PACKAGE_FBV is not set
# BR2_PACKAGE_IMAGEMAGICK is not set
# BR2_PACKAGE_SDL is not set
......@@ -428,6 +438,7 @@ BR2_PACKAGE_STRACE=y
#
# dbus not available (need expat or libxml2)
#
# BR2_PACKAGE_DEVMEM2 is not set
#
# dmraid requires a toolchain with LARGEFILE support
......@@ -455,6 +466,10 @@ BR2_PACKAGE_STRACE=y
#
# gvfs requires a toolchain with LARGEFILE and WCHAR support
#
#
# hdparm requires a toolchain with LARGEFILE support
#
# BR2_PACKAGE_HWDATA is not set
# BR2_PACKAGE_I2C_TOOLS is not set
# BR2_PACKAGE_INPUT_EVENT_DAEMON is not set
......@@ -751,7 +766,7 @@ BR2_PACKAGE_LIBPCAP=y
# BR2_PACKAGE_ARGP_STANDALONE is not set
# BR2_PACKAGE_LIBATOMIC_OPS is not set
# BR2_PACKAGE_LIBCAP is not set
# BR2_PACKAGE_LIBDAEMON is not set
BR2_PACKAGE_LIBDAEMON=y
BR2_PACKAGE_LIBELF=y
# BR2_PACKAGE_LIBEVENT is not set
# BR2_PACKAGE_LIBEV is not set
......@@ -788,7 +803,7 @@ BR2_PACKAGE_NCURSES=y
# BR2_PACKAGE_NCURSES_TARGET_FORM is not set
# BR2_PACKAGE_NCURSES_TARGET_MENU is not set
# BR2_PACKAGE_NEWT is not set
# BR2_PACKAGE_PCRE is not set
BR2_PACKAGE_PCRE=y
# BR2_PACKAGE_POPT is not set
BR2_PACKAGE_READLINE=y
# BR2_PACKAGE_SLANG is not set
......@@ -822,6 +837,7 @@ BR2_PACKAGE_READLINE=y
# BR2_PACKAGE_AVAHI is not set
# BR2_PACKAGE_AXEL is not set
# BR2_PACKAGE_BLUEZ_UTILS is not set
# BR2_PACKAGE_BOA is not set
#
# bind requires a toolchain with LARGEFILE and IPV6 support
......@@ -839,7 +855,8 @@ BR2_PACKAGE_BRIDGE_UTILS=y
#
# BR2_PACKAGE_CIFS_UTILS is not set
# BR2_PACKAGE_CUPS is not set
# BR2_PACKAGE_DHCPDUMP is not set
# BR2_PACKAGE_DHCP is not set
BR2_PACKAGE_DHCPDUMP=y
# BR2_PACKAGE_DNSMASQ is not set
BR2_PACKAGE_DROPBEAR=y
BR2_PACKAGE_DROPBEAR_DISABLE_REVERSEDNS=y
......@@ -852,6 +869,7 @@ BR2_PACKAGE_DROPBEAR_SMALL=y
#
BR2_PACKAGE_ETHTOOL=y
# BR2_PACKAGE_HOSTAPD is not set
BR2_PACKAGE_IFPLUGD=y
#
# iperf requires a toolchain with C++ support enabled
......@@ -868,6 +886,7 @@ BR2_PACKAGE_IPROUTE2=y
#
# Kismet requires a toolchain with C++ support enabled
#
# BR2_PACKAGE_LIGHTTPD is not set
# BR2_PACKAGE_LINKS is not set
# BR2_PACKAGE_LRZSZ is not set
# BR2_PACKAGE_MII_DIAG is not set
......@@ -875,6 +894,15 @@ BR2_PACKAGE_IPROUTE2=y
# BR2_PACKAGE_MUTT is not set
# BR2_PACKAGE_NBD is not set
# BR2_PACKAGE_NCFTP is not set
# BR2_PACKAGE_NETCAT is not set
#
# netkitbase requires a toolchain with RPC support
#
#
# netkittelnet requires a toolchain with RPC support
#
# BR2_PACKAGE_NETPLUG is not set
# BR2_PACKAGE_NETSNMP is not set
# BR2_PACKAGE_NETSTAT_NAT is not set
......@@ -920,6 +948,9 @@ BR2_PACKAGE_RSYNC=y
BR2_PACKAGE_TCPDUMP=y
# BR2_PACKAGE_TCPDUMP_SMB is not set
# BR2_PACKAGE_TCPREPLAY is not set
# BR2_PACKAGE_TFTPD is not set
# BR2_PACKAGE_THTTPD is not set
# BR2_PACKAGE_TINYHTTPD is not set
# BR2_PACKAGE_TN5250 is not set
# BR2_PACKAGE_TTCP is not set
......@@ -929,6 +960,7 @@ BR2_PACKAGE_TCPDUMP=y
# BR2_PACKAGE_VPNC is not set
# BR2_PACKAGE_VSFTPD is not set
# BR2_PACKAGE_VTUN is not set
# BR2_PACKAGE_WGET is not set
# BR2_PACKAGE_WIRELESS_TOOLS is not set
# BR2_PACKAGE_WPA_SUPPLICANT is not set
# BR2_PACKAGE_XL2TP is not set
......@@ -938,6 +970,10 @@ BR2_PACKAGE_TCPDUMP=y
#
# BR2_PACKAGE_IPKG is not set
#
# rpm requires libneon with SSL, XML and ZLIB support
#
#
# Real-Time
#
......@@ -947,6 +983,8 @@ BR2_PACKAGE_TCPDUMP=y
# Shell and utilities
#
# BR2_PACKAGE_AT is not set
# BR2_PACKAGE_BASH is not set
# BR2_PACKAGE_DASH is not set
# BR2_PACKAGE_DIALOG is not set
# BR2_PACKAGE_FILE is not set
......@@ -957,6 +995,7 @@ BR2_PACKAGE_TCPDUMP=y
# BR2_PACKAGE_LOGROTATE is not set
BR2_PACKAGE_SCREEN=y
# BR2_PACKAGE_SUDO is not set
# BR2_PACKAGE_WHICH is not set
# BR2_PACKAGE_XMLSTARLET is not set
#
......@@ -970,7 +1009,20 @@ BR2_PACKAGE_SCREEN=y
#
# attr requires a toolchain with LARGEFILE support
#
#
# bootutils requires a toolchain with LARGEFILE support
#
# BR2_PACKAGE_HTOP is not set
# BR2_PACKAGE_MODULE_INIT_TOOLS is not set
# BR2_PACKAGE_PROCPS is not set
# BR2_PACKAGE_PSMISC is not set
# BR2_PACKAGE_RSYSLOG is not set
#
# syslogd requires a toolchain with LARGEFILE support
#
# BR2_PACKAGE_SYSVINIT is not set
#
# util-linux requires a toolchain with LARGEFILE + WCHAR support
......@@ -980,8 +1032,10 @@ BR2_PACKAGE_SCREEN=y
# Text editors and viewers
#
# BR2_PACKAGE_ED is not set
# BR2_PACKAGE_NANO is not set
# BR2_PACKAGE_LESS is not set
BR2_PACKAGE_NANO=y
# BR2_PACKAGE_UEMACS is not set
# BR2_PACKAGE_VIM is not set
#
# Filesystem images
......
patches/g45memtest/0001-board-9g45ek-fix-ddr-config-for-WRS-V3.patch
View file @ b81a5d0e
From f87ac48aaf4ec7726391b87577fceede1b561228 Mon Sep 17 00:00:00 2001
From 6c56f4f07d953d33a90584dd15360f8d572483a4 Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Thu, 15 Sep 2011 23:41:14 +0200
Subject: [PATCH 1/6] board 9g45ek: fix ddr config for WRS-V3
Subject: [PATCH 01/19] board 9g45ek: fix ddr config for WRS-V3
---
board/at91sam9g45ek/at91sam9g45ek.c | 2 +-
......@@ -81,5 +81,5 @@ index 550aea4..a4a168f 100644
#define AT91C_DDRC2_NR_12 (0x1 << 2) // (HDDRSDRC2) 12 Bits
#define AT91C_DDRC2_NR_13 (0x2 << 2) // (HDDRSDRC2) 13 Bits
--
1.7.7.2
1.7.9.5
patches/g45memtest/0002-printf-added-files-from-pptp-unchanged.patch
View file @ b81a5d0e
From c27eea873f4a7dd9bea3da51b8e4aba27b9e52fc Mon Sep 17 00:00:00 2001
From b257bbfacdfa9475ca0a812a64d6ab59de9ea440 Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 6 Mar 2012 10:18:59 +0100
Subject: [PATCH 2/6] printf: added files from pptp, unchanged
Subject: [PATCH 02/19] printf: added files from pptp, unchanged
---
lib/diag-printf.c | 34 ++++++++++++++++++++++++++
lib/printf-mini.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 103 insertions(+), 0 deletions(-)
2 files changed, 103 insertions(+)
create mode 100644 lib/diag-printf.c
create mode 100644 lib/printf-mini.c
......@@ -126,5 +126,5 @@ index 0000000..d68c848
+ return str - buf;
+}
--
1.7.7.2
1.7.9.5
patches/g45memtest/0003-printf-fixes-and-addition-to-makefile.patch
View file @ b81a5d0e
From 3ebc7c415750ffcd7cf4241010027773609e6919 Mon Sep 17 00:00:00 2001
From dc2e9ac1fcca99e6c4924714f26cf85a87e3259c Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 6 Mar 2012 10:37:27 +0100
Subject: [PATCH 3/6] printf: fixes and addition to makefile
Subject: [PATCH 03/19] printf: fixes and addition to makefile
---
include/pp_printf.h | 9 +++++++++
......@@ -78,5 +78,5 @@ index 2a46204..8810324 100644
#include "main.h"
#include "dbgu.h"
--
1.7.7.2
1.7.9.5
patches/g45memtest/0004-version-add-tmpconfig-to-ignore-list.patch 0 → 100644
View file @ b81a5d0e
From 391890df3ca410003b51bf45a4b17a5a8e22a588 Mon Sep 17 00:00:00 2001
From: Benoit Rat <benoit@sevensols.com>
Date: Fri, 23 Mar 2012 13:42:57 +0100
Subject: [PATCH 04/19] version: add tmpconfig to ignore list
---
.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitignore b/.gitignore
index d78652e..a973a59 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,3 +21,4 @@ binaries
*.o
tags
*.swp
+.tmpconfig*
--
1.7.9.5
patches/g45memtest/0005-version-Improve-tracking-bin-versions-adding-git-ver.patch 0 → 100644
View file @ b81a5d0e
From c28fc11363fb86c25b447817a6554874ad65f09a Mon Sep 17 00:00:00 2001
From: Benoit Rat <benoit@sevensols.com>
Date: Wed, 28 Mar 2012 18:54:06 +0200
Subject: [PATCH 05/19] version: Improve tracking bin versions adding git
version in Makefile
---
.gitignore | 1 +
Makefile | 25 ++++++++++++++++++++++++-
main.c | 6 ++++++
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/.gitignore b/.gitignore
index a973a59..8b91fe5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -22,3 +22,4 @@ binaries
tags
*.swp
.tmpconfig*
+version.c
diff --git a/Makefile b/Makefile
index 6216632..c61ee3e 100644
--- a/Makefile
+++ b/Makefile
@@ -220,7 +220,7 @@ include driver/driver.mk
SRCS := $(COBJS-y:.o=.c)
-OBJS := $(SOBJS-y) $(COBJS-y)
+OBJS := $(SOBJS-y) $(COBJS-y) version.o
INCL=board/$(BOARD)
@@ -273,6 +273,29 @@ PHONY:=all gen_bin
all: PrintFlags gen_bin ChkFileSize
+## If not git is found
+ifeq ($(shell git status -s | grep -v "fatal*"),)
+version.c: $(SOBJS-y) $(COBJS-y)
+ @echo "/**" > $@
+ @echo " * File automatically generated by Makefile (DO NOT MODIFIED)\n *\n * To use this you in a c code just add the following lines:\n * " >> $@
+ @echo "\textern const char build_time[];\n\textern const char git_user[];\n\textren const char git_revision[];\n * " >> $@
+ @echo "**/" >> $@
+ @echo 'const char build_time[] = __DATE__ " @ " __TIME__ ;' >> $@
+ @echo "const char git_user[] = \"$(shell id -nu)\";" >> $@
+ @echo "const char git_revision[] = \"\";" >> $@
+ @echo "" >> $@
+else
+version.c: $(SOBJS-y) $(COBJS-y) .git/HEAD .git/index
+ @echo "/**" > $@
+ @echo " * File automatically generated by Makefile (DO NOT MODIFIED)\n *\n * To use this you in a c code just add the following lines:\n * " >> $@
+ @echo "\textern const char build_time[];\n\textern const char git_user[];\n\textren const char git_revision[];\n * " >> $@
+ @echo "**/" >> $@
+ @echo 'const char build_time[] = __DATE__ " @ " __TIME__ ;' >> $@
+ @echo "const char git_user[] = \"$(shell git config --get user.name)\";" >> $@
+ @echo "const char git_revision[] = \"$(shell git rev-parse HEAD)$(shell if git status -s > /dev/null; then echo '+'; fi;)\";" >> $@
+ @echo "" >> $@
+endif
+
PrintFlags:
@echo as FLAGS
@echo ========
diff --git a/main.c b/main.c
index 8810324..0ea1716 100644
--- a/main.c
+++ b/main.c
@@ -83,6 +83,10 @@ void Wait(unsigned int count)
/*------------------------------------------------------------------------------*/
int main(void)
{
+ extern const char build_time[];
+ extern const char git_user[];
+ extern const char git_revision[];
+
/*
* ================== 1st step: Hardware Initialization =================
*
@@ -92,6 +96,8 @@ int main(void)
hw_init();
#endif
+ pp_printf("Compiled by %s (%s)\r\ngit rev:%s\r\n\r\n",git_user,build_time,git_revision);
+
#ifdef CONFIG_USER_HW_INIT
user_hw_init();
#endif
--
1.7.9.5
patches/g45memtest/0006-leds-Correct-FPGA-LED-problems-and-add-CPU-LED-durin.patch 0 → 100644
View file @ b81a5d0e
From 4a94ffdd4e78d50d24669f2646b3648bc93a51c4 Mon Sep 17 00:00:00 2001
From: Benoit Rat <benoit@sevensols.com>
Date: Wed, 28 Mar 2012 19:19:46 +0200
Subject: [PATCH 06/19] leds: Correct FPGA LED problems, and add CPU LED
during booting
---
board/at91sam9g45ek/at91sam9g45ek.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/board/at91sam9g45ek/at91sam9g45ek.c b/board/at91sam9g45ek/at91sam9g45ek.c
index 8569231..83c2c29 100644
--- a/board/at91sam9g45ek/at91sam9g45ek.c
+++ b/board/at91sam9g45ek/at91sam9g45ek.c
@@ -80,6 +80,17 @@ void hw_init(void)
};
/*
+ * Configure LED GPIOs
+ */
+ const struct pio_desc led_gpio[] = {
+ {"D11", AT91C_PIN_PA(0), 0, PIO_OPENDRAIN, PIO_OUTPUT}, //Switch on D11 when booting start.
+ {"D12", AT91C_PIN_PA(1), 1, PIO_OPENDRAIN, PIO_OUTPUT}, //Setup D12 such to use when the programs end loading.
+ {"DDone", AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_INPUT}, //Setup FPGA LED Done in read mode
+ {"DInit", AT91C_PIN_PA(3), 0, PIO_DEFAULT, PIO_INPUT} //Setup FPGA LED Init in read mode
+ };
+ pio_setup(led_gpio);
+
+ /*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
--
1.7.9.5
patches/g45memtest/0008-boot-disable-watchdog-asap.patch 0 → 100644
View file @ b81a5d0e
From 3c96273023f759800c3cb3309ac1ef8a83fe7f04 Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 10 Apr 2012 13:00:22 +0200
Subject: [PATCH 08/19] boot: disable watchdog asap
---
crt0_gnu.S | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/crt0_gnu.S b/crt0_gnu.S
index c00b717..0a9079b 100644
--- a/crt0_gnu.S
+++ b/crt0_gnu.S
@@ -105,6 +105,11 @@ _relocate_to_sram:
ldr pc, =_setup_clocks
#endif /* CONFIG_FLASH */
+ /* disable watchdog */
+ ldr r1, =0xFFFFFD44
+ mov r2, #0x00008000
+ str r2, [r1]
+
ldr r4, = lowlevel_clock_init
mov lr, pc
bx r4
--
1.7.9.5
patches/g45memtest/0009-boot-added-flip_leds-count-in-assembler.patch 0 → 100644
View file @ b81a5d0e
From a6f38ea81c99fca8ad2c67b0b03d97c16fe97d94 Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 10 Apr 2012 13:04:09 +0200
Subject: [PATCH 09/19] boot: added flip_leds(count) in assembler
---
crt0_gnu.S | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/crt0_gnu.S b/crt0_gnu.S
index 0a9079b..784c9ce 100644
--- a/crt0_gnu.S
+++ b/crt0_gnu.S
@@ -74,6 +74,35 @@ irq_vector:
b irq_vector
fiq_vector:
b fiq_vector
+
+/*
+ * First of all, write a procedure, that can be called from C or asm,
+ * to flip leds a number of times, after a small delay
+ */
+
+flip_leds: /* input: r0 is the count of flips */
+
+ /* a delay */
+ ldr r1, =200
+1: subs r1, r1, #1
+ bne 1b
+
+ ldr r1, =0xfffff200 /* PIOA */
+ mov r2, #3 /* bit 0 and 1: both leds */
+
+ str r2, [r1] /* enable */
+ str r2, [r1, #0x10] /* output enable */
+ cmp r0, #0
+ beq 2f
+0: str r2, [r1, #0x34] /* output clear (led on) */
+ str r2, [r1, #0x30] /* output set (led off) */
+ subs r0, r0, #1
+ bne 0b
+
+2: bx lr
+
+.ltorg
+
reset_vector:
/* Init the stack */
--
1.7.9.5
patches/g45memtest/0010-boot-Run-a-test-pattern-between-clock-configuration.patch 0 → 100644
View file @ b81a5d0e
From b24256ae1eab66b12e361dc0e7873d081275ac24 Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 10 Apr 2012 13:40:59 +0200
Subject: [PATCH 10/19] boot: Run a test pattern between clock configuration
---
crt0_gnu.S | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/crt0_gnu.S b/crt0_gnu.S
index 784c9ce..bc54989 100644
--- a/crt0_gnu.S
+++ b/crt0_gnu.S
@@ -79,7 +79,6 @@ fiq_vector:
* First of all, write a procedure, that can be called from C or asm,
* to flip leds a number of times, after a small delay
*/
-
flip_leds: /* input: r0 is the count of flips */
/* a delay */
@@ -139,10 +138,20 @@ _relocate_to_sram:
mov r2, #0x00008000
str r2, [r1]
+ /* test 4x the flip_leds procedure */
+ mov r0, #0x4
+ bl flip_leds
+
+ /* Call the lowlevel clock init function in ./driver/pmc.c */
ldr r4, = lowlevel_clock_init
mov lr, pc
bx r4
+ /* test 8x the flip_leds procedure */
+ mov r0, #0x8
+ bl flip_leds
+
+
#if 0
_setup_clocks:
/* Test if main oscillator is enabled */
--
1.7.9.5
patches/g45memtest/0011-boot-Correct-crash-due-to-an-Atmel-bug-during-boot-w.patch 0 → 100644
View file @ b81a5d0e
From 00b15b66a2bde319a0e4ba592a26f921d542cfca Mon Sep 17 00:00:00 2001
From: Benoit Rat <benoit@sevensols.com>
Date: Wed, 11 Apr 2012 17:25:28 +0200
Subject: [PATCH 11/19] boot: Correct crash due to an Atmel bug during boot
when PLL clock is already used as master clock
---
driver/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver/pmc.c b/driver/pmc.c
index 1a09b9c..189d1c9 100644
--- a/driver/pmc.c
+++ b/driver/pmc.c
@@ -96,7 +96,7 @@ void lowlevel_clock_init()
/*
* After stablization, switch to 12MHz Main Oscillator
*/
- if ((read_pmc(PMC_MCKR) & AT91C_PMC_CSS) != AT91C_PMC_CSS_SLOW_CLK) {
+ if ((read_pmc(PMC_MCKR) & AT91C_PMC_CSS) == AT91C_PMC_CSS_SLOW_CLK) {
write_pmc(PMC_MCKR, AT91C_PMC_CSS_MAIN_CLK | AT91C_PMC_PRES_CLK);
while (!(read_pmc(PMC_SR) & AT91C_PMC_MCKRDY))
;
--
1.7.9.5
patches/g45memtest/0012-Improve-makefile-to-only-take-the-gitversion-of-curr.patch 0 → 100644
View file @ b81a5d0e
From 8083ba2049c07ce9f939819ce3016912d256019f Mon Sep 17 00:00:00 2001
From: Benoit Rat <benoit@sevensols.com>
Date: Wed, 11 Apr 2012 17:25:28 +0200
Subject: [PATCH 12/19] Improve makefile to only take the gitversion of
current directory
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index c61ee3e..fd7f16e 100644
--- a/Makefile
+++ b/Makefile
@@ -292,7 +292,7 @@ version.c: $(SOBJS-y) $(COBJS-y) .git/HEAD .git/index
@echo "**/" >> $@
@echo 'const char build_time[] = __DATE__ " @ " __TIME__ ;' >> $@
@echo "const char git_user[] = \"$(shell git config --get user.name)\";" >> $@
- @echo "const char git_revision[] = \"$(shell git rev-parse HEAD)$(shell if git status -s > /dev/null; then echo '+'; fi;)\";" >> $@
+ @echo "const char git_revision[] = \"$(shell git log --abbrev-commit --pretty=oneline -1 . | cut -d" " -f1)$(shell if git status -s > /dev/null; then echo '+'; fi;)\";" >> $@
@echo "" >> $@
endif
--
1.7.9.5
patches/g45memtest/0013-add-simple-script-to-compile-for-DF-and-NF.patch 0 → 100644
View file @ b81a5d0e
From eaa9bd4511b69b6097726b68957fa7da5a44323f Mon Sep 17 00:00:00 2001
From: Benoit Rat <benoit@sevensols.com>
Date: Fri, 11 May 2012 12:36:25 +0200
Subject: [PATCH 13/19] add simple script to compile for DF and NF
---
build.sh | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100755 build.sh
diff --git a/build.sh b/build.sh
new file mode 100755
index 0000000..a9711d9
--- /dev/null
+++ b/build.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+showhelp()
+{
+ echo "Usage: $0 [options]"
+ echo "options:"
+ echo " --help: show this little help"
+ echo " --df: compile only for dataflash"
+ echo " --nf: compile only for nandflash"
+}
+
+
+
+case "$1" in
+ --help) showhelp;;
+ --nf) yes "" | make at91sam9g45nf_defconfig > /dev/null; make;;
+ --df) yes "" | make at91sam9g45df_defconfig > /dev/null; make;;
+ *) yes "" | make at91sam9g45df_defconfig > /dev/null; make; yes "" | make at91sam9g45nf_defconfig > /dev/null; make;;
+esac
+
+
--
1.7.9.5
patches/g45memtest/0014-Correct-a-bug-in-makefile.patch 0 → 100644
View file @ b81a5d0e
From 5006567aeb801664a861ffe05337943c89dcae60 Mon Sep 17 00:00:00 2001
From: Benoit Rat <benoit@sevensols.com>
Date: Fri, 11 May 2012 12:48:13 +0200
Subject: [PATCH 14/19] Correct a bug in makefile
---
Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index fd7f16e..88dfffc 100644
--- a/Makefile
+++ b/Makefile
@@ -285,14 +285,14 @@ version.c: $(SOBJS-y) $(COBJS-y)
@echo "const char git_revision[] = \"\";" >> $@
@echo "" >> $@
else
-version.c: $(SOBJS-y) $(COBJS-y) .git/HEAD .git/index
+version.c: $(SOBJS-y) $(COBJS-y) .git/HEAD .git/index Makefile
@echo "/**" > $@
@echo " * File automatically generated by Makefile (DO NOT MODIFIED)\n *\n * To use this you in a c code just add the following lines:\n * " >> $@
@echo "\textern const char build_time[];\n\textern const char git_user[];\n\textren const char git_revision[];\n * " >> $@
@echo "**/" >> $@
@echo 'const char build_time[] = __DATE__ " @ " __TIME__ ;' >> $@
@echo "const char git_user[] = \"$(shell git config --get user.name)\";" >> $@
- @echo "const char git_revision[] = \"$(shell git log --abbrev-commit --pretty=oneline -1 . | cut -d" " -f1)$(shell if git status -s > /dev/null; then echo '+'; fi;)\";" >> $@
+ @echo "const char git_revision[] = \"$(shell git log --abbrev-commit --pretty=oneline -1 . | cut -d" " -f1)$(shell if git status -s > /dev/null; then echo '+'; else echo ''; fi;)\";" >> $@
@echo "" >> $@
endif
--
1.7.9.5
patches/g45memtest/0004-memtest.c-copied-from-barebox-our-version.patch → patches/g45memtest/0015-memtest-copied-from-barebox-our-version.patch
View file @ b81a5d0e
From 425ef2fa1550b9e480167f8b125adb897f281798 Mon Sep 17 00:00:00 2001
From 80b81d783772a87000356f126cb47dc429a95f3d Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 6 Mar 2012 10:42:17 +0100
Subject: [PATCH 4/6] memtest.c: copied from barebox (our version)
Subject: [PATCH 15/19] memtest: copied from barebox (our version)
---
lib/memtest.c | 355 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 355 insertions(+), 0 deletions(-)
1 file changed, 355 insertions(+)
create mode 100644 lib/memtest.c
diff --git a/lib/memtest.c b/lib/memtest.c
......@@ -370,5 +370,5 @@ index 0000000..d9c8b3d
+BAREBOX_CMD_END
+
--
1.7.7.2
1.7.9.5
patches/g45memtest/0005-memtest-fix-it-and-add-to-makefile.patch → patches/g45memtest/0016-memtest-fix-it-and-add-to-makefile.patch
View file @ b81a5d0e
From 74e27efd703fbafab08c28c7f7d0eb1aaae7db8e Mon Sep 17 00:00:00 2001
From fa3b681d37c9787473f4ed8fc33205471696db8d Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 6 Mar 2012 11:38:53 +0100
Subject: [PATCH 5/6] memtest: fix it and add to makefile
Subject: [PATCH 16/19] memtest: fix it and add to makefile
---
lib/libc.mk | 1 +
lib/memtest.c | 85 +++++++++++++++++++++++---------------------------------
lib/memtest.c | 85 ++++++++++++++++++++++++---------------------------------
2 files changed, 36 insertions(+), 50 deletions(-)
diff --git a/lib/libc.mk b/lib/libc.mk
......@@ -191,5 +191,5 @@ index d9c8b3d..52542c9 100644
-BAREBOX_CMD_END
-
--
1.7.7.2
1.7.9.5
patches/g45memtest/0006-main-call-memtest.patch → patches/g45memtest/0017-main-call-memtest.patch
View file @ b81a5d0e
From cf60a3a806e75315e39610d40607d76efcc5816c Mon Sep 17 00:00:00 2001
From 5f895df9f30230375cbbf2320a7c8af00d852fc2 Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 6 Mar 2012 11:39:13 +0100
Subject: [PATCH 6/6] main: call memtest
Subject: [PATCH 17/19] main: call memtest
---
main.c | 92 +++-------------------------------------------------------------
1 files changed, 4 insertions(+), 88 deletions(-)
main.c | 93 ++++------------------------------------------------------------
1 file changed, 5 insertions(+), 88 deletions(-)
diff --git a/main.c b/main.c
index 8810324..e4a6956 100644
index 0ea1716..60f3fe7 100644
--- a/main.c
+++ b/main.c
@@ -83,6 +83,7 @@ void Wait(unsigned int count)
/*------------------------------------------------------------------------------*/
int main(void)
{
+ extern void mem_test(unsigned long ini, unsigned long end);
@@ -86,6 +86,8 @@ int main(void)
extern const char build_time[];
extern const char git_user[];
extern const char git_revision[];
+
+ extern void mem_test(unsigned long ini, unsigned long end);
/*
* ================== 1st step: Hardware Initialization =================
*
@@ -101,92 +102,7 @@ int main(void)
@@ -107,92 +109,7 @@ int main(void)
load_1wire_info();
#endif
......@@ -116,5 +117,5 @@ index 8810324..e4a6956 100644
+ return 0; /* not reached */
}
--
1.7.7.2
1.7.9.5
patches/g45memtest/0019-memtest-Add-CPU-LED-switching-to-memtest.patch 0 → 100644
View file @ b81a5d0e
From 78f344309e4fa491efd1240f481d15c00f6d47b2 Mon Sep 17 00:00:00 2001
From: Benoit Rat <benoit@sevensols.com>
Date: Mon, 2 Apr 2012 15:43:17 +0200
Subject: [PATCH 19/19] memtest: Add CPU LED switching to memtest
---
lib/memtest.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/lib/memtest.c b/lib/memtest.c
index 4366171..20c5e45 100644
--- a/lib/memtest.c
+++ b/lib/memtest.c
@@ -26,6 +26,7 @@
#include <pp_printf.h>
#include <dbgu.h>
#include <debug.h>
+#include <gpio.h>
//#include <stdlib.h>
/* BEGIN HACKS - to compile barebox code out of barebox */
@@ -120,6 +121,8 @@ int mem_test_integrity(ulong _start, ulong _end, ulong pattern)
//Increment actual read value and decrement write value.
val += incr;
val_next -= incr;
+
+ if((*addr % (1024*100)) == 0) pio_set_value(AT91C_PIN_PA(0),*addr % (2048*100)); //Blinking light while testing
}
printf("\tOK\r\n");
@@ -401,6 +404,10 @@ int mem_test(ulong _start, ulong _end, ulong pattern_unused)
printf ("OK: bus line, address line and integrity are OK\n\r\n\r");
printf ("Now it will continue to check integrity with various patterns. (Ctrl+C to exit)...\n\r");
+ pio_set_value(AT91C_PIN_PA(0),1);
+ pio_set_value(AT91C_PIN_PA(1),0);
+
+
return mem_test_integrity(_start,_end,pattern_unused);
}
--
1.7.9.5
patches/g45memtest/README.md 0 → 100644
View file @ b81a5d0e
G45 memtest
============
The test is inspired from the one in barebox
It has been improved[^1] and now check:
* Data lines
* Address lines
* Memory integrity
* holding counters
* holding anti-counters
* Random patterns
You can find the source on my github: https://github.com/neub/wrs-sw-at91bootstrap/tree/memtest
[^1]: http://www.barrgroup.com/Embedded-Systems/How-To/Memory-Test-Suite-C
patches/kernel/v2.6.39/0005-fix-nand-parition-layout-and-usb-vbus.patch 0 → 100644
View file @ b81a5d0e
From 6f5a77b2cc2b1253ee5a4a9fb578c3bd4e5a8e60 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Thu, 31 May 2012 13:26:20 +0200
Subject: [PATCH] Fix NAND partition layout to avoid overwriting barebox
environment and USB VBus pin connection
---
arch/arm/mach-at91/board-sam9m10g45ek.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index d0e1e67..2ce5751 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -81,7 +81,7 @@ static struct at91_usbh_data __initdata ek_usbh_hs_data = {
* USB HS Device port
*/
static struct usba_platform_data __initdata ek_usba_udc_data = {
- .vbus_pin = AT91_PIN_PB19,
+ .vbus_pin = AT91_PIN_PB8,
};
@@ -131,14 +131,14 @@ static struct at91_eth_data __initdata ek_macb_data = {
*/
static struct mtd_partition __initdata ek_nand_partition[] = {
{
- .name = "Partition 1",
+ .name = "kernel",
.offset = 0,
.size = SZ_64M,
},
{
- .name = "Partition 2",
+ .name = "rootfs",
.offset = MTDPART_OFS_NXTBLK,
- .size = MTDPART_SIZ_FULL,
+ .size = SZ_128M,
},
};
--
1.7.5.4
tools/.gitignore
View file @ b81a5d0e
load-lm32
load-virtex
mapper
wmapper
spi-pll
wmapper
\ No newline at end of file
tools/Makefile
View file @ b81a5d0e
......@@ -16,17 +16,11 @@ STRIP = $(CROSS_COMPILE)strip
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
LIB = libtools.a
LDFLAGS = -L.
LIBOBJ = lm32-loader.o load-fpga.o
PROGS = mapper wmapper
LDFLAGS = -L. -ltools
all: $(PROGS)
PROGS = load-lm32 load-virtex spi-pll mapper wmapper
$(PROGS):
all: $(LIB) $(PROGS)
$(PROGS): $(LIB)
$(LIB): $(LIBOBJ)
$(AR) r $@ $^
tools/spi-pll.c deleted 100644 → 0
View file @ b1f76342
/*
* Trivial pll programmer using an spi controoler.
* PLL is AD9516, SPI is opencores
* Tomasz Wlostowski, Alessandro Rubini, 2011, for CERN.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdint.h>
#include <string.h>
#include <fcntl.h>
#include <errno.h>
#include <time.h>
#include <sys/time.h>
#include <sys/mman.h>
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
#endif
#define WRS3_SPI_BASE 0x10000000 /* FIXME */
static void ud(int usecs) /* horrible udelay thing without scheduling */
{
struct timeval tv1, tv2;
gettimeofday(&tv1, NULL);
do
gettimeofday(&tv2, NULL);
while ((tv2.tv_sec - tv1.tv_sec) * 1000*1000
+ tv2.tv_usec - tv1.tv_usec < usecs);
}
/*
* SPI stuff, used by later code
*/
#define SPI_REG_RX0 0
#define SPI_REG_TX0 0
#define SPI_REG_RX1 4
#define SPI_REG_TX1 4
#define SPI_REG_RX2 8
#define SPI_REG_TX2 8
#define SPI_REG_RX3 12
#define SPI_REG_TX3 12
#define SPI_REG_CTRL 16
#define SPI_REG_DIVIDER 20
#define SPI_REG_SS 24
#define SPI_CTRL_ASS (1<<13)
#define SPI_CTRL_IE (1<<12)
#define SPI_CTRL_LSB (1<<11)
#define SPI_CTRL_TXNEG (1<<10)
#define SPI_CTRL_RXNEG (1<<9)
#define SPI_CTRL_GO_BSY (1<<8)
#define SPI_CTRL_CHAR_LEN(x) ((x) & 0x7f)
static int oc_spi_base;
static inline void ocspi_write(int addr, uint32_t val)
{
if (!oc_spi_base)
return;
*(uint32_t *)(oc_spi_base + addr) = val;
printf("%08x := %08x\n", oc_spi_base + addr, val);
}
static inline uint32_t ocspi_read(int addr)
{
uint32_t val;
if (!oc_spi_base)
return -1;
val =*(uint32_t *)(oc_spi_base + addr);
printf("%08x = %08x\n", oc_spi_base + addr, val);
return val;
}
int oc_spi_init(char *prgname, uint32_t base_addr)
{
int pagesize = getpagesize(); /* can't fail */
int fdmem;
void *addr;
/* /dev/mem for mmap of both gpio and spi1 */
if ((fdmem = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
fprintf(stderr, "%s: /dev/mem: %s\n",
prgname, strerror(errno));
return -1;
}
/* map a whole page (4kB, but we called getpagesize to know it) */
addr = mmap(0, pagesize, PROT_READ | PROT_WRITE,
MAP_SHARED, fdmem,
base_addr & (~(pagesize-1)));
if (addr == MAP_FAILED) {
fprintf(stderr, "%s: mmap(/dev/mem): %s\n",
prgname, strerror(errno));
return -1;
}
close(fdmem);
oc_spi_base = (int)addr + (base_addr & (pagesize-1));
ocspi_write(SPI_REG_DIVIDER, 1000);
return 0;
}
int oc_spi_txrx(int ss, int nbits, uint32_t in, uint32_t *out)
{
uint32_t rval;
if (!out)
out = &rval;
ocspi_write( SPI_REG_CTRL,
SPI_CTRL_ASS | SPI_CTRL_CHAR_LEN(nbits)
| SPI_CTRL_TXNEG);
ocspi_write( SPI_REG_TX0, in);
ocspi_write( SPI_REG_SS, (1 << ss));
ocspi_write( SPI_REG_CTRL,
SPI_CTRL_ASS | SPI_CTRL_CHAR_LEN(nbits)
| SPI_CTRL_TXNEG | SPI_CTRL_GO_BSY);
while(ocspi_read(SPI_REG_CTRL) & SPI_CTRL_GO_BSY)
;
*out = ocspi_read(SPI_REG_RX0);
return 0;
}
#define CS_PLL 0 /* AD9516 on SPI CS0 */
/*
* AD9516 stuff, using SPI, used by later code.
* "reg" is 12 bits, "val" is 8 bits, but both are better used as int
*/
static void ad9516_write_reg(int reg, int val)
{
oc_spi_txrx(CS_PLL, 24, (reg << 8) | val, NULL);
}
static int ad9516_read_reg(int reg)
{
uint32_t rval;
oc_spi_txrx(CS_PLL, 24, (reg << 8) | (1 << 23), &rval);
return rval & 0xff;
}
/* FIXME: table of registers .... */
struct adregval {
int reg;
int val;
};
static struct adregval ad9516_regs[0];
static int ad9516_init(FILE *fout)
{
int i;
if (fout)
fprintf(fout, "Initializing AD9516 PLL...\n");
ad9516_write_reg(0x000, 0x99);
ad9516_write_reg(0x232, 0x01);
if (ad9516_read_reg(0x3) != 0xc3) {
fprintf(stderr,"Error: AD9516 PLL not responding.\n");
return -1;
}
for (i=0; i < ARRAY_SIZE(ad9516_regs); i++)
ad9516_write_reg (ad9516_regs[i].reg, ad9516_regs[i].val);
while ((ad9516_read_reg(0x1f) & 1) == 0)
ud(100);
// sync channels
ad9516_write_reg(0x230, 1);
ad9516_write_reg(0x232, 1);
ad9516_write_reg(0x230, 0);
ad9516_write_reg(0x232, 1);
if (fout)
fprintf(fout, "AD9516 locked.\n");
return 0;
}
/*
* That's it. Here's our main function
*/
int main(int argc, char **argv)
{
if (oc_spi_init(argv[0], WRS3_SPI_BASE) < 0)
exit(1);
if (ad9516_init(stdout) < 0)
exit(1);
/* Wow! Nothing to do! */
exit(0);
}
usb-loader/.gitignore
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version.c
mch_flasher
samba_applets/isp-project/*/bin/
usb-loader/Makefile
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OBJS=mch_flasher.o serial_linux.o version.o
OUTPUT=mch_flasher
OBJS = mch_flasher.o serial_linux.o
FLASHER = mch_flasher
all: $(OBJS)
${CC} -o $(OUTPUT) $(OBJS)
all: $(FLASHER)
$(FLASHER): $(OBJS)
${CC} -o $@ $(OBJS)
version.c: ../.git/HEAD ../.git/index
echo "/**" > $@
echo " * File automatically generated by Makefile (DO NOT MODIFIED)\n *\n * To use this you in a c code just add the following lines:\n * " >> $@
echo "\textern const char build_time[];\n\textern const char git_user[];\n\textren const char git_revision[];\n * " >> $@
echo "**/" >> $@
echo 'const char build_time[] = __DATE__ " @ " __TIME__ ;' >> $@
echo "const char git_user[] = \"$(shell git config --get user.name)\";" >> $@
echo "const char git_revision[] = \"$(shell git rev-parse HEAD)\";" >> $@
echo "" >> $@
clean:
rm -f $(OBJS) $(FLASHER) *~
rm -f version.c $(OBJS) $(OUTPUT):q:q
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usb-loader/samba_applets/at91lib/boards/at91sam9g45-ek/board_memories.c
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......@@ -38,6 +38,7 @@
#include <board.h>
#include <pio/pio.h>
#include "board_memories.h"
#include <utility/trace.h>
/*
Macros:
......@@ -49,6 +50,12 @@
#define READ(peripheral, register) (peripheral->register)
#define WRITE(peripheral, register, value) (peripheral->register = value)
//------------------------------------------------------------------------------
// External definitions
//------------------------------------------------------------------------------
#ifndef AT91C_DDRC2_NR_XX
#define AT91C_DDRC2_NR_XX AT91C_DDRC2_NR_13 /*This value should be 13 for WRS3-18*/
#endif
//------------------------------------------------------------------------------
// Internal functions
......@@ -78,20 +85,20 @@ void BOARD_RemapRam()
}
void BOARD_ConfigureVddMemSel(unsigned char VddMemSel)
{
if (VddMemSel == VDDMEMSEL_3V3) {
AT91C_BASE_MATRIX->MATRIX_EBICSA |= (1 << 16);
AT91C_BASE_MATRIX->MATRIX_EBICSA &= ~(1 << 17);
}
else {
AT91C_BASE_MATRIX->MATRIX_EBICSA &= ~(1 << 16);
AT91C_BASE_MATRIX->MATRIX_EBICSA &= ~(1 << 17);
}
}
void BOARD_ConfigureVddMemSel(unsigned char VddMemSel)
{
if (VddMemSel == VDDMEMSEL_3V3) {
AT91C_BASE_MATRIX->MATRIX_EBICSA |= (1 << 16);
AT91C_BASE_MATRIX->MATRIX_EBICSA &= ~(1 << 17);
}
else {
AT91C_BASE_MATRIX->MATRIX_EBICSA &= ~(1 << 16);
AT91C_BASE_MATRIX->MATRIX_EBICSA &= ~(1 << 17);
}
}
//------------------------------------------------------------------------------
/// Configure DDR
//------------------------------------------------------------------------------
......@@ -102,6 +109,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
int i;
volatile unsigned int cr = 0;
unsigned short ddrc_dbw = 0;
unsigned int ba_offset;
switch (busWidth) {
case 16:
......@@ -114,6 +122,9 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
break;
}
// Enable DDR2 clock x2 in PMC
WRITE(AT91C_BASE_PMC, PMC_SCER, AT91C_PMC_DDR);
......@@ -135,11 +146,28 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
// 4. Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR.
WRITE(pDdrc, HDDRSDRC2_CR, AT91C_DDRC2_NC_DDR10_SDR9 | // 10 column bits (1K)
AT91C_DDRC2_NR_14 | // 14 row bits (8K)
AT91C_DDRC2_NR_XX | // 13 row bits (8K)
AT91C_DDRC2_CAS_3 | // CAS Latency 3
AT91C_DDRC2_DLL_RESET_DISABLED
); // DLL not reset
/* compute BA[] offset according to CR configuration */
ba_offset = (READ(pDdrc, HDDRSDRC2_CR) & AT91C_DDRC2_NC) + 9; // number of column bits for DDR
ba_offset += ((READ(pDdrc, HDDRSDRC2_CR) & AT91C_DDRC2_NR) >> 2) + 11; // number of row bits
ba_offset += (ddrc_dbw & AT91C_DDRC2_DBW) ? 1 : 2; // bus width
TRACE_INFO("\tDDR2 Config: 0x%x (NC=%d, NR=%d, CAS=%d, ba_offset=%d) \n\r",
(READ(pDdrc, HDDRSDRC2_CR)),
(READ(pDdrc, HDDRSDRC2_CR) & AT91C_DDRC2_NC) + 9,
((READ(pDdrc, HDDRSDRC2_CR) & AT91C_DDRC2_NR) >> 2) + 11,
(READ(pDdrc, HDDRSDRC2_CR) & AT91C_DDRC2_CAS) >> 4,
ba_offset);
// assume timings for 7.5ns min clock period
WRITE(pDdrc, HDDRSDRC2_T0PR, AT91C_DDRC2_TRAS_6 | // 6 * 7.5 = 45 ns
AT91C_DDRC2_TRCD_2 | // 2 * 7.5 = 15 ns
......@@ -189,7 +217,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
// Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x4000000)) = 0;
*((unsigned int *)((unsigned char *)pDdr + (0x2 << ba_offset))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
......@@ -198,7 +226,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
// Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x6000000)) = 0;
*((unsigned int *)((unsigned char *)pDdr + (0x3 << ba_offset))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
......@@ -207,7 +235,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
// Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x2000000)) = 0;
*((unsigned int *)((unsigned char *)pDdr + (0x1 << ba_offset))) = 0;
// wait 200 cycles min
for (i = 0; i < 10000; i++) {
......@@ -267,7 +295,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
// Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x2000000)) = 0;
*((unsigned int *)((unsigned char *)pDdr + (0x1 << ba_offset))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
......@@ -280,7 +308,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
// Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x6000000)) = 0;
*((unsigned int *)((unsigned char *)pDdr + (0x1 << ba_offset))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
......@@ -292,7 +320,7 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
*(pDdr) = 0;
// Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a
// refresh every 15.625 ¦Ìs or 7.81 ¦Ìs. With a 100MHz frequency, the refresh timer count register must to be set with
// refresh every 15.625 ns or 7.81 ns. With a 100MHz frequency, the refresh timer count register must to be set with
// (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 i.e. 0x030d.
// Set Refresh timer
......@@ -520,6 +548,22 @@ void BOARD_ConfigureSdram(unsigned char busWidth)
//------------------------------------------------------------------------------
void BOARD_ConfigureNandFlash(unsigned char busWidth)
{
AT91C_BASE_MATRIX->MATRIX_EBICSA |= AT91C_EBI_CS3A_SM;
// Configure SMC
AT91C_BASE_SMC->SMC_SETUP3 = 0x00020002;
AT91C_BASE_SMC->SMC_PULSE3 = 0x04040404;
AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070007;
AT91C_BASE_SMC->SMC_CTRL3 = 0x00030003;
if (busWidth == 8) {
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
}
else if (busWidth == 16) {
AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
}
}
//------------------------------------------------------------------------------
......
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......@@ -318,6 +318,10 @@
#endif
#define DUMP_REG(structname, periph, reg) \
TRACE_INFO("%s%s = 0x%08x\r\n", #periph,#reg, \
((AT91PS_##structname )(AT91C_BASE_##periph)) -> structname##_##reg);
//------------------------------------------------------------------------------
// Exported variables
//------------------------------------------------------------------------------
......
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