Commit cd46c8cd authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

On boot time try locking SPLL until it is locked

We have to try until 10MHz and 1-PPS is there in GrandMaster mode.
Otherwise we won't have timing at all.
parent 6affdf37
......@@ -73,8 +73,14 @@ int hal_init_timing()
if(tmo_expired(&lock_tmo))
{
TRACE(TRACE_ERROR, "Can't lock the PLL. If running in the GrandMaster mode, are you sure the 1-PPS and 10 MHz reference clock signals are properly connected?");
return -1;
TRACE(TRACE_ERROR, "Can't lock the PLL. If running in the GrandMaster mode, are you sure the 1-PPS and 10 MHz reference clock signals are properly connected?, retrying...");
if(timing_mode == HAL_TIMING_MODE_GRAND_MASTER) {
/*ups... something went wrong, but instead of giving-up, try one more time*/
rts_set_mode(RTS_MODE_GM_EXTERNAL);
tmo_init(&lock_tmo, LOCK_TIMEOUT_EXT, 0);
}
else
return -1;
}
if(rts_get_state(&pstate) < 0)
......
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