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White Rabbit Switch - Software
Commit cf2081c2 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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userspace/libswitchhw: added shw_pps_gen_enable_output()

parent c6e901fa
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Showing with 27 additions and 9 deletions
userspace/include/hw/pps_gen.h
View file @ cf2081c2
......@@ -10,6 +10,7 @@ int shw_pps_gen_init();
int shw_pps_gen_adjust_nsec(int32_t how_much);
int shw_pps_gen_adjust_utc(int64_t how_much);
int shw_pps_gen_busy();
int shw_pps_gen_sync_external_pps();
int shw_pps_gen_enable_output(int enable);
#endif
userspace/include/hw/pps_gen_regs.h
View file @ cf2081c2
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : ../../../software/include/hw/pps_gen_regs.h
* Author : auto-generated by wbgen2 from wrsw_pps_gen.wb
* Created : Mon May 9 00:28:48 2011
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Mon Apr 23 22:33:01 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#include <inttypes.h>
......@@ -67,6 +67,12 @@
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
......
userspace/libswitchhw/pps_gen.c
View file @ cf2081c2
......@@ -60,7 +60,18 @@ int shw_pps_gen_adjust_utc(int64_t how_much)
/* Returns 1 when the adjustment operation is not yet finished */
int shw_pps_gen_busy()
{
return _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CR) & PPSG_CR_CNT_ADJ ? 0 : 1;
uint32_t cr = _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CR);
return cr& PPSG_CR_CNT_ADJ ? 0 : 1;
}
\ No newline at end of file
/* Enables/disables PPS output */
int shw_pps_gen_enable_output(int enable)
{
uint32_t escr = _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR);
if(enable)
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR, escr | PPSG_ESCR_PPS_VALID)
else
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ESCR, escr & ~PPSG_ESCR_PPS_VALID);
return 0;
}
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