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White Rabbit Switch - Software
Commits
d16d88b1
Commit
d16d88b1
authored
Mar 29, 2012
by
Benoit Rat
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usb-loader: configure to fit our DDR parameters, use define to configure from outside
parent
3d99e051
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1 changed file
with
32 additions
and
18 deletions
+32
-18
board_memories.c
...ba_applets/at91lib/boards/at91sam9g45-ek/board_memories.c
+32
-18
No files found.
usb-loader/samba_applets/at91lib/boards/at91sam9g45-ek/board_memories.c
View file @
d16d88b1
...
...
@@ -38,6 +38,7 @@
#include <board.h>
#include <pio/pio.h>
#include "board_memories.h"
#include <utility/trace.h>
/*
Macros:
...
...
@@ -49,6 +50,12 @@
#define READ(peripheral, register) (peripheral->register)
#define WRITE(peripheral, register, value) (peripheral->register = value)
//------------------------------------------------------------------------------
// External definitions
//------------------------------------------------------------------------------
#ifndef AT91C_DDRC2_NR_VAL
#define AT91C_DDRC2_NR_VAL 13 //This value should be 13 for WRS3-18
#endif
//------------------------------------------------------------------------------
// Internal functions
...
...
@@ -78,20 +85,20 @@ void BOARD_RemapRam()
}
void
BOARD_ConfigureVddMemSel
(
unsigned
char
VddMemSel
)
{
if
(
VddMemSel
==
VDDMEMSEL_3V3
)
{
AT91C_BASE_MATRIX
->
MATRIX_EBICSA
|=
(
1
<<
16
);
AT91C_BASE_MATRIX
->
MATRIX_EBICSA
&=
~
(
1
<<
17
);
}
else
{
AT91C_BASE_MATRIX
->
MATRIX_EBICSA
&=
~
(
1
<<
16
);
AT91C_BASE_MATRIX
->
MATRIX_EBICSA
&=
~
(
1
<<
17
);
}
}
void
BOARD_ConfigureVddMemSel
(
unsigned
char
VddMemSel
)
{
if
(
VddMemSel
==
VDDMEMSEL_3V3
)
{
AT91C_BASE_MATRIX
->
MATRIX_EBICSA
|=
(
1
<<
16
);
AT91C_BASE_MATRIX
->
MATRIX_EBICSA
&=
~
(
1
<<
17
);
}
else
{
AT91C_BASE_MATRIX
->
MATRIX_EBICSA
&=
~
(
1
<<
16
);
AT91C_BASE_MATRIX
->
MATRIX_EBICSA
&=
~
(
1
<<
17
);
}
}
//------------------------------------------------------------------------------
/// Configure DDR
//------------------------------------------------------------------------------
...
...
@@ -135,18 +142,25 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
// 4. Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR.
WRITE
(
pDdrc
,
HDDRSDRC2_CR
,
AT91C_DDRC2_NC_DDR10_SDR9
|
// 10 column bits (1K)
AT91C_DDRC2_NR_
13
|
// 14 row bits (8K)
AT91C_DDRC2_NR_
VAL
|
// 13 row bits (8K)
AT91C_DDRC2_CAS_3
|
// CAS Latency 3
AT91C_DDRC2_DLL_RESET_DISABLED
);
// DLL not reset
TRACE_INFO
(
"
\t
DDR2 Config: 0x%x (NC=%d, NR=%d, CAS=%d)
\n\r
"
,
READ
(
pDdrc
,
HDDRSDRC2_CR
),
(
READ
(
pDdrc
,
HDDRSDRC2_CR
)
&
AT91C_DDRC2_NC
)
+
9
,
((
READ
(
pDdrc
,
HDDRSDRC2_CR
)
&
AT91C_DDRC2_NR
)
>>
2
)
+
11
,
(
READ
(
pDdrc
,
HDDRSDRC2_CR
)
&
AT91C_DDRC2_CAS
)
>>
4
);
// assume timings for 7.5ns min clock period
WRITE
(
pDdrc
,
HDDRSDRC2_T0PR
,
AT91C_DDRC2_TRAS_6
|
// 6 * 7.5 = 45 ns
AT91C_DDRC2_TRCD_2
|
// 2 * 7.5 = 15 ns
AT91C_DDRC2_TWR_2
|
// 2 * 7.5 = 15 ns
AT91C_DDRC2_TRC_8
|
// 8 * 7.5 = 60 ns
AT91C_DDRC2_TRP_2
|
// 2 * 7.5 = 15 ns
AT91C_DDRC2_TRRD_
2
|
// 2 * 7.5 = 1
5 ns
AT91C_DDRC2_TRRD_
1
|
// 1 * 7.5 = 7.
5 ns
AT91C_DDRC2_TWTR_1
|
// 1 clock cycle
AT91C_DDRC2_TMRD_2
);
// 2 clock cycles
...
...
@@ -156,8 +170,8 @@ void BOARD_ConfigureDdram(unsigned char ddrModel, unsigned char busWidth)
AT91C_DDRC2_TRFC_14
<<
0
);
// 14 * 7.5 = 105 ns (must be 105 ns for 512M DDR)
WRITE
(
pDdrc
,
HDDRSDRC2_T2PR
,
AT91C_DDRC2_TRTP_1
|
// 1 * 7.5 = 7.5 ns
AT91C_DDRC2_TRPA_
2
|
AT91C_DDRC2_TXARDS_
8
|
// 7 clock cycles
AT91C_DDRC2_TRPA_
0
|
AT91C_DDRC2_TXARDS_
7
|
// 7 clock cycles
AT91C_DDRC2_TXARD_2
);
// 2 clock cycles
// Step 3: An NOP command is issued to the DDR2-SDRAM to enable clock.
...
...
Write
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