vtuCore: improve style.

16df5e32 · Tristan Gingold · 1110276b · 16df5e32
Commit 16df5e32 authored Apr 23, 2020 by Tristan Gingold
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Showing with 31 additions and 27 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +31 -27

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -684,7 +684,7 @@ entity vtuSeq is
        OutputEnable2 : in std_logic;
        Shifter1Ena : out std_logic := '0';
        Shifter2Ena : out std_logic := '0';
-        SwitchtoHT : out std_logic := '0';
+        SwitchtoHT : out std_logic := '0';    -- Select B or HT output.
        wValueOne : in std_logic;
        WindowDone : in std_logic;
        CounterRst : out std_logic := '0';
@@ -723,23 +723,23 @@ begin
              --  Wait for Sync.
              Shifter1Ena <= '1';
              Shifter2Ena <= '0';
-              SwitchtoHT   <= '0';
-              CounterRst <= '0';
+              SwitchtoHT  <= '0';
+              CounterRst  <= '0';
              Run <= '0';
              state <= S_waitSync;
            elsif Start = '1' and SyncPulse = '1' then
              --  Start and sync: directly run.
              Shifter1Ena <= '1';
              Shifter2Ena <= '1';
-              SwitchtoHT   <= '0';
-              CounterRst <= '0';
+              SwitchtoHT  <= '0';
+              CounterRst  <= '0';
              Run <= '1';
              state <= S_BValue;
            else
              Shifter1Ena <= '1';
              Shifter2Ena <= '0';
-              SwitchtoHT   <= '0';
-              CounterRst <= '0';
+              SwitchtoHT  <= '0';
+              CounterRst  <= '0';
              Run <= '0';
              state <= Idle;
            end if;
@@ -749,8 +749,8 @@ begin
              --  Run.
              Shifter1Ena <= '1';
              Shifter2Ena <= '1';
-              SwitchtoHT   <= '0';
-              CounterRst <= '0';
+              SwitchtoHT  <= '0';
+              CounterRst  <= '0';
              Run <= '1';
              state <= S_BValue;
            else
@@ -760,32 +760,35 @@ begin

          when S_BValue =>
            if OutputEnable1 = '1' and wValueOne = '0' then
+              --  First pulse sent, send the others.
              Shifter1Ena <= '1';
              Shifter2Ena <= '1';
-              SwitchtoHT   <= '1';
-              CounterRst <= '0';
+              SwitchtoHT  <= '1';
+              CounterRst  <= '0';
              state <= S_HTValue;
            elsif OutputEnable1 = '1' and wValueOne = '1' then
+              --  First pulse sent, but there is only one pulse to send.
+              --  Back to idle.
              Shifter1Ena <= '1';
              Shifter2Ena <= '0';
-              SwitchtoHT   <= '0';
-              CounterRst <= '1';
+              SwitchtoHT  <= '0';
+              CounterRst  <= '1';
              Run <= '0';
              state <= Idle;
            elsif Start = '1' and SyncPulse = '0' then
              --  Restart, wait for sync
              Shifter1Ena <= '1';
              Shifter2Ena <= '0';
-              SwitchtoHT   <= '0';
-              CounterRst <= '1';
+              SwitchtoHT  <= '0';
+              CounterRst  <= '1';
              Run <= '0';
              state <= S_waitSync;
            elsif Start = '1' and SyncPulse = '1' then
              --  Restart, run.
              Shifter1Ena <= '1';
              Shifter2Ena <= '1';
-              SwitchtoHT   <= '0';
-              CounterRst <= '1';
+              SwitchtoHT  <= '0';
+              CounterRst  <= '1';
              state <= S_BValue;
            else
              CounterRst <= '0';
@@ -797,8 +800,8 @@ begin
              --  Done.
              Shifter1Ena <= '1';
              Shifter2Ena <= '0';
-              SwitchtoHT   <= '0';
-              CounterRst <= '1';
+              SwitchtoHT  <= '0';
+              CounterRst  <= '1';
              Run <= '0';
              state <= Idle;
            else
@@ -1483,15 +1486,16 @@ begin
             DataOutPlayMem when Mode = C_Code_ctuAsVtu_control2_mode_playMemory else
             DataOut_seq;

+  --  Pulse detected.
  SyncPulse <= SyncPulse_i;

-  process (htValue , htValuePlusOne , SwitchHTeffective)
+  process (htValue, htValuePlusOne, SwitchHTeffective)
  begin
     case SwitchHTeffective is
       when '0' =>
-         htValue_effective(63 downto 0) <=  htValue(63 downto 0);
+         htValue_effective <=  htValue;
       when others =>
-         htValue_effective(63 downto 0) <=  htValuePlusOne(63 downto 0);
+         htValue_effective <=  htValuePlusOne;
     end case;
   end process;

@@ -1502,9 +1506,9 @@ begin
  begin
   if Run_n = '1' then
      visual_B_SwitchHTFF_Q <= '0';
-   elsif Clk'event and Clk = '1' then
+    elsif Clk'event and Clk = '1' then
      if HTSwitchEna = '1' then
-        visual_B_SwitchHTFF_Q <= (SwitchHTeffective_n);
+        visual_B_SwitchHTFF_Q <= SwitchHTeffective_n;
      end if;
    end if;
  end process;
@@ -1583,7 +1587,7 @@ begin

  process (wValue_effective, CZero)
   begin
-      if wValue_effective(63 downto 0) = CZero(63 downto 0) then
+      if wValue_effective = (63 downto 0 => '0') then
        wValueOne <= '1';
      else
        wValueOne <= '0';
@@ -1625,9 +1629,9 @@ begin
  begin
     case SetStartData is
       when '0' =>
-         DataInHTSyncLess(7 downto 0) <=  DataOutHTSyncLess(7 downto 0);
+         DataInHTSyncLess <=  DataOutHTSyncLess;
       when others =>
-         DataInHTSyncLess(7 downto 0) <=  SyncLessStartData(7 downto 0);
+         DataInHTSyncLess <=  SyncLessStartData;
     end case;
   end process;