Fixed some constraints. Some paths not constrained; eg no clocks on tmg_io pins,…

Fixed some constraints. Some paths not constrained; eg no clocks on tmg_io pins, many CDCs go from fast into slow domains need reviewing to ensure pulse widths can be captured and latched.

Fixed some constraints. Some paths not constrained; eg no clocks on tmg_io pins,…
Fixed some constraints. Some paths not constrained; eg no clocks on tmg_io pins, many CDCs go from fast into slow domains need reviewing to ensure pulse widths can be captured and latched.
28cb43c6 · John Gill · ef60281b · 28cb43c6 · 28cb43c6
Commit 28cb43c6 authored Mar 25, 2020 by John Gill
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Showing with 8 additions and 7 deletions

wr2rf_maxdelays.tcl hdl/syn/wr2rf_maxdelays.tcl +2 -2

wr2rf_vme.xdc hdl/syn/wr2rf_vme.xdc +6 -5

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--- a/hdl/syn/wr2rf_maxdelays.tcl
+++ b/hdl/syn/wr2rf_maxdelays.tcl
@@ -20,7 +20,7 @@ foreach endcell [get_cells -hier -filter {name=~*sync_*edge.sync0_reg}] {
 	    set startcell [get_property PARENT_CELL [get_pins $startpin]]
 	    set startclks [get_clocks -of_objects [get_cells $startcell]]
 	    if {$startclks eq ""} {
-		puts "ERROR: NO  CLOCK: $startcell"
+		puts "ERROR: NO  CLOCK for $startcell from $endpin"
 	    } else {
 		set startperiods [get_property PERIOD [get_clocks $startclks]]
 		set minstartperiod [tcl::mathfunc::min {*}$startperiods]
@@ -35,7 +35,7 @@ foreach endcell [get_cells -hier -filter {name=~*sync_*edge.sync0_reg}] {
 	    set startport [lindex $startpins 0]
 	    set startclks [get_clocks -of_objects [get_ports $startport]]
 	    if {$startclks eq ""} {
-		puts "ERROR: NO  CLOCK: $startport"
+		puts "ERROR: NO  CLOCK for $startport from $endpin"
 	    } else {
 		set startperiods [get_property PERIOD [get_clocks $startclks]]
 		set minstartperiod [tcl::mathfunc::min {*}$startperiods]

--- a/hdl/syn/wr2rf_vme.xdc
+++ b/hdl/syn/wr2rf_vme.xdc
@@ -1378,16 +1378,17 @@ create_clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLKFABRI
 create_clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLKFABRIC]
 create_clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLK]

-# Create generated clocks on the output of the BUGMUX and then physically exclude them
-create_generated_clock -name clk_dmtd_bgmux -divide_by 1 -add -master_clock clk_dmtd -source [get_ports {clk_dmtd_62m5_p_i}] [get_pins {inst_BUFGMUX_CTRL/O}]
-create_generated_clock -name clk_sys_bgmux  -divide_by 1 -add -master_clock clk_sys  -source [get_ports {clk_sys_62m5_p_i}]  [get_pins {inst_BUFGMUX_CTRL/O}] 
+# Create generated clocks on the output of the BUGMUX and then physically exclude them, See AR #59484
+create_generated_clock -name clk_dmtd_bgmux -divide_by 1      -source [get_ports {clk_dmtd_62m5_p_i}] [get_pins {inst_BUFGMUX_CTRL/O}]
+create_generated_clock -name clk_sys_bgmux  -divide_by 1 -add -source [get_ports {clk_sys_62m5_p_i}]  [get_pins {inst_BUFGMUX_CTRL/O}] 
+
 set_clock_groups -physically_exclusive -group clk_sys_bgmux -group clk_dmtd_bgmux

 ###################
 # False paths
 ###################
-set_false_path -from [get_ports clk_sys_62m5_p_i]  -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]
-set_false_path -from [get_ports clk_dmtd_62m5_p_i] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]
+set_false_path -from [get_pins {inst_BUFGMUX_CTRL/O}] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]
+set_false_path -from [get_pins {inst_BUFGMUX_CTRL/O}] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]

 # False path all inputs to synchronizer (pos/negedge searching) registers - is there a better way?
 # set_false_path -to [get_cells -hier -filter {name=~*sync_posedge.sync0_reg}]