vtu_blk: fix data order for oserdes. Change the test for small delays.

4d1219e4 · Tristan Gingold · 656077a2 · 4d1219e4 · 4d1219e4 · 4d1219e4
Commit 4d1219e4 authored Apr 02, 2020 by Tristan Gingold
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Showing with 13 additions and 10 deletions

trigunit_regs.cheby hdl/rtl/trigunit_regs.cheby +1 -1

vtu_blk.vhd hdl/rtl/vtu_blk.vhd +8 -8

tb_vtu.vhd hdl/testbench/vtu/tb_vtu.vhd +4 -1

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--- a/hdl/rtl/trigunit_regs.cheby
+++ b/hdl/rtl/trigunit_regs.cheby
@@ -38,7 +38,7 @@ memory-map:
              description: Start ignored as VTU not ready
              comment: >
                The start pulse hasn't been transferred to the VTU because
-                it wasn't ready.  Either the RF clock is was not present, or
+                it wasn't ready.  Either the RF clock was not present, or
                the start pulse came too early. Changed when the next
                start pulse is detected.
              range: 6

--- a/hdl/rtl/vtu_blk.vhd
+++ b/hdl/rtl/vtu_blk.vhd
@@ -507,14 +507,14 @@ begin
            TQ => open,                     -- 1-bit output: 3-state control
            CLK => clk_rf_i,               -- 1-bit input: High speed clock
            CLKDIV => clk_vtu_i,            -- 1-bit input: Divided clock
-            D1 => sync_data_out(0),         -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
-            D2 => sync_data_out(1),
-            D3 => sync_data_out(2),
-            D4 => sync_data_out(3),
-            D5 => sync_data_out(4),
-            D6 => sync_data_out(5),
-            D7 => sync_data_out(6),
-            D8 => sync_data_out(7),
+            D1 => sync_data_out(7),         -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+            D2 => sync_data_out(6),
+            D3 => sync_data_out(5),
+            D4 => sync_data_out(4),
+            D5 => sync_data_out(3),
+            D6 => sync_data_out(2),
+            D7 => sync_data_out(1),
+            D8 => sync_data_out(0),
            OCE => '1',                     -- 1-bit input: Output data clock enable
            RST => rst_vtu,                 -- 1-bit input: Reset
            SHIFTIN1 => '0',                -- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)

--- a/hdl/testbench/vtu/tb_vtu.vhd
+++ b/hdl/testbench/vtu/tb_vtu.vhd
@@ -64,8 +64,11 @@ begin
        write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_TRIGDIAG + ADDR_VTUDIAG_REGS_CONTROL, x"0000");

        --  Program the vtu
+        --  Delay between start and the first pulse.
        write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_BVALUEOFFLINE, x"0000_0000_0000_0020");
-        write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEOFFLINE, x"0000_0000_0000_0030");
+        --  Delay between the pulses.
+        write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEOFFLINE, x"0000_0000_0000_0008");
+        --  Number of pulses.
        write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEOFFLINE, x"0000_0000_0000_0004");

        --  Windowed mode, enable.