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wr2rf-vme
Commit 5d8857a2 authored by John Robert Gill's avatar John Robert Gill
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hdl/rtl/registers/trigunit_regs.vhd
View file @ 5d8857a2
-- Do not edit. Generated on Wed Mar 24 16:37:30 2021 by jgill
-- Do not edit. Generated on Mon Mar 29 11:21:46 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/registers/wr2rf_init_regs.cheby
View file @ 5d8857a2
......@@ -307,6 +307,20 @@ memory-map:
name: profile
description: Select dds profile
range: 6-4
- reg:
name: dds_ioupdate
description: dds (AD9910) control signals
access: rw
width: 16
children:
- field:
name: fdelay
description: nanosecond delay of the dds_ioupdate signal
range: 3-0
- field:
name: odelay
description: odelay value, steps of 78 ps
range: 8-4
- reg:
name: dds_status
description: dds (AD9910) status signals
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ 5d8857a2
-- Do not edit. Generated on Wed Mar 24 16:37:31 2021 by jgill
-- Do not edit. Generated on Mon Mar 29 11:21:47 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......
hdl/rtl/registers/wr2rf_rfnco_regs.vhd
View file @ 5d8857a2
-- Do not edit. Generated on Wed Mar 24 16:37:32 2021 by jgill
-- Do not edit. Generated on Mon Mar 29 11:21:48 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i RFNCO.cheby --gen-hdl
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ 5d8857a2
-- Do not edit. Generated on Wed Mar 24 16:37:31 2021 by jgill
-- Do not edit. Generated on Mon Mar 29 11:21:47 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ 5d8857a2
This diff is collapsed.
hdl/rtl/wr2rf_dds.vhd
View file @ 5d8857a2
......@@ -35,14 +35,22 @@ use work.wishbone_pkg.all;
entity wr2rf_dds is
port (
clk250m_i : in std_logic;
clk62m5_i : in std_logic;
clk125m_i : in std_logic;
clk500m_i : in std_logic;
rst_clk62m5_i : in std_logic;
rst_clk125m_i : in std_logic;
ioupdate_fdelay_i : in std_logic_vector(3 downto 0);
ioupdate_odelay_i : in std_logic_vector(4 downto 0);
dds_ioupdate_i : in std_logic;
dds_ioupdate_o : out std_logic;
dds_sync_p_o : out std_logic;
dds_sync_n_o : out std_logic );
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of wr2rf_dds : entity is "yes";
end entity;
architecture rtl of wr2rf_dds is
......@@ -53,10 +61,23 @@ architecture rtl of wr2rf_dds is
-- timing on our DDSs. It is _not_ used to synchronise the
-- ad9910 outputs - see ioupdate for that
signal dds_sync : std_logic;
-- ioupdate fine delay
signal ioupdate_delayed_r : std_logic;
signal ioupdate_delayed_h : std_logic;
signal ioupdate_delayed_hh : std_logic;
signal ioupdate_delayed_hhh : std_logic;
signal ioupdate_pattern : std_logic_vector(23 downto 0);
signal ioupdate_pattern_r : std_logic_vector(23 downto 0);
signal ioupdate_fdelay_r : std_logic_vector(3 downto 0);
signal dds_ioupdate_fdelay : std_logic_vector(7 downto 0);
signal dds_ioupdate_fdelay_r : std_logic_vector(7 downto 0);
signal dds_ioupdate_fdelayed : std_logic;
signal dds_ioupdate : std_logic;
begin
-- We need the DDS SYNC_CLK to be one quarter of the DDS SYSCLK frequency (1 GHz)
-- We need the DDS SYNC_CLK to be one sixteenth of the DDS SYSCLK frequency (1 GHz)
oddr_inst : oddr
generic map (
ddr_clk_edge => "same_edge",
......@@ -65,18 +86,114 @@ begin
port map (
d1 => '1',
d2 => '0',
c => clk250m_i,
c => clk62m5_i,
ce => '1',
q => dds_sync,
r => '0',
s => '0' );
dds_sync_i : obufds
generic map(
generic map(
slew => "FAST" )
port map(
o => dds_sync_p_o,
ob => dds_sync_n_o,
i => dds_sync );
----------------------------------------------------
-- Now for ioupdate
----------------------------------------------------
ioupdate_pattern <= std_logic_vector(unsigned'(X"0000FF") sll to_integer(unsigned(ioupdate_fdelay_r)));
dds_ioupdate_fdelay <= ioupdate_pattern_r(7 downto 0) when ioupdate_delayed_r = '1' and ioupdate_delayed_h = '0' else
ioupdate_pattern_r(15 downto 8) when ioupdate_delayed_h = '1' and ioupdate_delayed_hh = '0' else
ioupdate_pattern_r(23 downto 16) when ioupdate_delayed_hh = '1' and ioupdate_delayed_hhh = '0' else (others => '0');
process (clk125m_i) is
begin
if rising_edge(clk125m_i) then
ioupdate_delayed_r <= dds_ioupdate_i;
ioupdate_delayed_h <= ioupdate_delayed_r;
ioupdate_delayed_hh <= ioupdate_delayed_h;
ioupdate_delayed_hhh <= ioupdate_delayed_hh;
ioupdate_pattern_r <= ioupdate_pattern;
ioupdate_fdelay_r <= ioupdate_fdelay_i;
dds_ioupdate_fdelay_r <= dds_ioupdate_fdelay;
end if;
end process;
inst_ioupdate_OSERDESE2 : oserdese2
generic map (
DATA_RATE_OQ => "DDR", -- DDR, SDR
DATA_RATE_TQ => "SDR", -- DDR, BUF, SDR
DATA_WIDTH => 8, -- Parallel data width (2-8,10,14)
INIT_OQ => '0', -- Initial value of OQ output (1'b0,1'b1)
INIT_TQ => '0', -- Initial value of TQ output (1'b0,1'b1)
SERDES_MODE => "MASTER", -- MASTER, SLAVE
SRVAL_OQ => '0', -- OQ output value when SR is used (1'b0,1'b1)
SRVAL_TQ => '0', -- TQ output value when SR is used (1'b0,1'b1)
TBYTE_CTL => "FALSE", -- Enable tristate byte operation (FALSE, TRUE)
TBYTE_SRC => "FALSE", -- Tristate byte source (FALSE, TRUE)
TRISTATE_WIDTH => 1 ) -- 3-state converter width (1,4)
port map (
OFB => open, -- 1-bit output: Feedback path for data
OQ => dds_ioupdate_fdelayed, -- 1-bit output: Data path output
SHIFTOUT1 => open, -- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT2 => open,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => clk500m_i, -- 1-bit input: High speed clock
CLKDIV => clk125m_i, -- 1-bit input: Divided clock
D1 => dds_ioupdate_fdelay_r(0), -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D2 => dds_ioupdate_fdelay_r(1),
D3 => dds_ioupdate_fdelay_r(2),
D4 => dds_ioupdate_fdelay_r(3),
D5 => dds_ioupdate_fdelay_r(4),
D6 => dds_ioupdate_fdelay_r(5),
D7 => dds_ioupdate_fdelay_r(6),
D8 => dds_ioupdate_fdelay_r(7),
OCE => '1', -- 1-bit input: Output data clock enable
RST => rst_clk125m_i, -- 1-bit input: Reset
SHIFTIN1 => '0', -- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN2 => '0',
T1 => '0', -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' ); -- 1-bit input: 3-state clock enable
--
inst_sync_ODELAYE2 : ODELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE)
DELAY_SRC => "ODATAIN", -- Delay input (ODATAIN, CLKIN)
HIGH_PERFORMANCE_MODE => "TRUE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
ODELAY_TYPE => "VAR_LOAD", -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
ODELAY_VALUE => 0, -- Output delay tap setting (0-31)
PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE
REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
SIGNAL_PATTERN => "DATA" ) -- DATA, CLOCK input signal
port map (
CNTVALUEOUT => open, -- output: Counter value output
DATAOUT => dds_ioupdate, -- output: Delayed data/clock output
C => clk125m_i, -- input: Clock input
CE => '0', -- input: Active high enable increment/decrement input
CINVCTRL => '0', -- input: Dynamic clock inversion input
CLKIN => '0', -- input: Clock delay input
CNTVALUEIN => ioupdate_odelay_i, -- input: Counter value input
INC => '0', -- input: Increment / Decrement tap delay input
LD => '1', -- input: Loads ODELAY_VALUE tap delay in VARIABLE mode
LDPIPEEN => '0', -- input: Enables the pipeline register to load data
ODATAIN => dds_ioupdate_fdelayed, -- input: Output delay data input
REGRST => rst_clk62m5_i ); -- input: Active-high reset tap-delay input
dds_ioupdate_inst : obuf
generic map(
DRIVE => 16,
slew => "FAST" )
port map(
o => dds_ioupdate_o,
i => dds_ioupdate );
end architecture;
hdl/rtl/wr2rf_regs_core.vhd
View file @ 5d8857a2
......@@ -130,6 +130,8 @@ entity wr2rf_regs_core is
dds_reset_o : out std_logic;
dds_ioupdate_o : out std_logic;
dds_profile_o : out std_logic_vector(2 downto 0);
dds_ioupdate_fdelay_o : out std_logic_vector(3 downto 0);
dds_ioupdate_odelay_o : out std_logic_vector(4 downto 0);
dds_sync_error_i : in std_logic;
ocxo_enabled_o : out std_logic;
......@@ -381,6 +383,8 @@ begin
init_dds_ctrl_reset_o => dds_reset_o,
init_dds_ctrl_ioupdate_o => dds_ioupdate_o,
init_dds_ctrl_profile_o => dds_profile_o,
init_dds_ioupdate_fdelay_o => dds_ioupdate_fdelay_o,
init_dds_ioupdate_odelay_o => dds_ioupdate_odelay_o,
init_dds_status_sync_error_i => dds_sync_error_i,
init_ocxo_ctrl_enable_o => ocxo_enabled_o,
......
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 5d8857a2
......@@ -43,8 +43,8 @@ entity wr2rf_vme is
generic (
g_simulation : integer := 0;
g_dpram_size : integer := 131072/4;
g_dpram_initf : string := "../../../../dependencies/wrpc-sw/wrc.bram";
-- g_dpram_initf : string := "";
-- g_dpram_initf : string := "../../../../dependencies/wrpc-sw/wrc.bram";
g_dpram_initf : string := "";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -639,10 +639,8 @@ architecture rtl of wr2rf_vme is
signal dds_ioupdate : std_logic;
signal dds_ioupdate_r : std_logic;
attribute IOB : string;
attribute keep : string;
attribute IOB of dds_ioupdate_r : signal is "true";
attribute keep of dds_ioupdate_r : signal is "true";
signal dds_ioupdate_fdelay : std_logic_vector(3 downto 0);
signal dds_ioupdate_odelay : std_logic_vector(4 downto 0);
-- ILA debug
signal ila_clk : std_logic;
......@@ -1057,9 +1055,17 @@ begin
wr2rf_dds_i : entity work.wr2rf_dds
port map (
clk250m_i => clk250m,
dds_sync_p_o => dds_sync_p_o,
dds_sync_n_o => dds_sync_n_o );
clk62m5_i => clk_sys_62m5,
clk125m_i => clk125m,
clk500m_i => clk500m,
rst_clk62m5_i => rst_sys,
rst_clk125m_i => rst_clk125m,
ioupdate_fdelay_i => dds_ioupdate_fdelay,
ioupdate_odelay_i => dds_ioupdate_odelay,
dds_ioupdate_i => dds_ioupdate_r,
dds_ioupdate_o => dds_ioupdate_o,
dds_sync_p_o => dds_sync_p_o,
dds_sync_n_o => dds_sync_n_o );
process (clk_sys_62m5) is
begin
......@@ -1068,8 +1074,6 @@ begin
end if;
end process;
dds_ioupdate_o <= dds_ioupdate_r;
wr2rf_rfchan_wrap_i : entity work.wr2rf_rfchan_wrap
port map (
clk125m_i => clk125m,
......@@ -1468,10 +1472,12 @@ begin
pll_main_locked_i => pll_main_stat_i(2),
pll_main_sync_o => pll_main_sync_o,
dds_reset_o => dds_reset_o,
dds_ioupdate_o => dds_ioupdate,
dds_profile_o => dds_profile_o,
dds_sync_error_i => dds_sync_error_i,
dds_reset_o => dds_reset_o,
dds_ioupdate_o => dds_ioupdate,
dds_profile_o => dds_profile_o,
dds_ioupdate_fdelay_o => dds_ioupdate_fdelay,
dds_ioupdate_odelay_o => dds_ioupdate_odelay,
dds_sync_error_i => dds_sync_error_i,
ocxo_enabled_o => ocxo_enabled,
ocxo_uptime_i => ocxo_uptime,
......
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