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Commit 5e15b48f authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: improve style.

parent 90d378bd
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Showing with 47 additions and 77 deletions
dependencies/vtu/rtl/vtuCore.vhd
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......@@ -519,32 +519,26 @@ end;
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.ctu_pckg.all;
entity vtuDataShifter is
generic (
N : INTEGER := 16;
generic (N : INTEGER := 16;
-- Number of bits of delay register. Minimum value: 4
g_DisableDoubleSync : std_logic := '1'
-- Avoid pulses between two words
);
port (
CoarseZero : out std_logic;
port (CoarseZero : out std_logic;
DataOut : out std_logic_vector(7 downto 0 );
OutputEnabled : out std_logic;
Clk : in std_logic;
Delay : in std_logic_vector(N - 1 downto 0 );
DataIn : in std_logic_vector(7 downto 0 );
Enabled : in std_logic;
SyncPulse : out std_logic
);
SyncPulse : out std_logic);
end vtuDataShifter;
architecture vtuDataShifter of vtuDataShifter is
signal SyncPulse_i : std_logic;
signal DataClean : std_logic_vector(7 downto 0 );
signal DataOut_i : std_logic_vector(7 downto 0 );
......@@ -580,79 +574,61 @@ architecture vtuDataShifter of vtuDataShifter is
Q : out std_logic
);
end component;
signal visual_B_Counter_cur_state : std_logic_vector((N - 4) - (0) + 1 - 1
downto 0 );
signal visual_B_Counter_next_state : std_logic_vector((N - 4) - (0) + 1 - 1
downto 0 );
signal visual_B_Counter_next_count : std_logic_vector((N - 4) - (0) + 1 - 1
downto 0 );
signal visual_B_CoarseDly_sub_dif_int : std_logic_vector((N - 4) - (0) + 1
downto 0 );
signal visual_B_CoarseDly_sub_tmp_a : std_logic_vector((N - 4) - (0) + 1 - 1
downto 0 );
signal visual_B_CoarseDly_sub_tmp_b : std_logic_vector((N - 4) - (0) + 1 - 1
downto 0 );
constant visual_B_CoarseDly_sub_zero : std_logic_vector((N - 4) - (0) + 1 - 1
downto 0 ) := (others => '0');
signal visual_B_Counter_cur_state : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_Counter_next_state : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_Counter_next_count : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_CoarseDly_sub_dif_int : std_logic_vector((N - 4) + 1 downto 0 );
signal visual_B_CoarseDly_sub_tmp_a : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_CoarseDly_sub_tmp_b : std_logic_vector((N - 4) + 1 - 1 downto 0 );
constant visual_B_CoarseDly_sub_zero : std_logic_vector((N - 4) + 1 - 1 downto 0 ) := (others => '0');
begin
B_ReadyFF: RSFF
port map (
Clk => Clk,
port map (Clk => Clk,
Set => SyncPulse_i,
Clr => Disabled,
Rst => open,
Q => Ready
);
Q => Ready);
B_OutGoodNext: RSFF
port map (
Clk => Clk,
port map (Clk => Clk,
Set => OutGood,
Clr => ClearOutGoodNext,
Rst => open,
Q => OutGoodNext
);
Q => OutGoodNext);
DataIn_clean <= clean_data(DataIn);
Sync_i <= ( DataIn_clean(7)) or ( DataIn_clean(6)) or ( DataIn_clean(5))
or ( DataIn_clean(4)) or ( DataIn_clean(3)) or ( DataIn_clean(2))
or ( DataIn_clean(1)) or ( DataIn_clean(0));
Sync_i <= DataIn_clean(7) or DataIn_clean(6) or DataIn_clean(5)
or DataIn_clean(4) or DataIn_clean(3) or DataIn_clean(2)
or DataIn_clean(1) or DataIn_clean(0);
CoarseCnt(N-4 downto 0) <= (visual_B_Counter_cur_state);
visual_B_Counter_next_state <= visual_B_Counter_next_count;
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (CntRst = '1') then
visual_B_Counter_cur_state <= (others => '0');
else
visual_B_Counter_cur_state <= visual_B_Counter_next_state;
end if;
end if;
if (Clk'event and Clk = '1') then
if CntRst = '1' then
visual_B_Counter_cur_state <= (others => '0');
else
visual_B_Counter_cur_state <= visual_B_Counter_next_state;
end if;
end if;
end process;
process (visual_B_Counter_cur_state )
begin
visual_B_Counter_next_count <= std_logic_vector(unsigned
(visual_B_Counter_cur_state) + 1);
visual_B_Counter_next_count <= std_logic_vector(unsigned (visual_B_Counter_cur_state) + 1);
end process;
CoarseDly_i(N-4 downto 0) <= Delay(N-1 downto 3);
FineDly(2 downto 0) <= Delay(2 downto 0);
CntRst <= ( SyncPulse_i) or ( Disabled);
CntRst <= ( SyncPulse_i) or ( Disabled);
process (C_Zero8 , DataOut_i , OutputEnabled_i)
process (C_Zero8, DataOut_i, OutputEnabled_i)
begin
case OutputEnabled_i is
when '0' =>
......@@ -662,9 +638,9 @@ begin
end case;
end process;
process (CoarseCnt , CoarseDly)
process (CoarseCnt, CoarseDly)
begin
if ((CoarseCnt(N-4 downto 0)) = (CoarseDly(N-4 downto 0))) then
if CoarseCnt(N-4 downto 0) = CoarseDly(N-4 downto 0) then
CoarseGood <= '1';
else
CoarseGood <= '0';
......@@ -673,13 +649,11 @@ begin
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Clk'event and Clk = '1') then
if (SyncPulse_i = '1') then
DataClean(7 downto 0) <= (DataIn_clean(7 downto 0));
end if;
end if;
end if;
end process;
process (OutGood , OutGoodNext , UseNextValue)
......@@ -708,50 +682,46 @@ begin
DataRaw(15 downto 8) <= DataClean(7 downto 0);
DataRaw(7 downto 0) <= C_Zero8(7 downto 0);
C_Zero8(7 downto 0) <= (others => '0');
C_Zero8(7 downto 0) <= (others => '0');
SyncPulse <= SyncPulse_i;
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Clk'event and Clk = '1') then
Sync_prev <= (Sync_i);
end if;
end if;
end process;
OutGood <= ( CoarseGood) and ( Ready);
OutGood <= ( CoarseGood) and ( Ready);
process (CoarseDly_i , CZeroDly)
begin
if ((CoarseDly_i(N-4 downto 0)) = (CZeroDly(N-4 downto 0))) then
if CoarseDly_i(N-4 downto 0) = CZeroDly(N-4 downto 0) then
CoarseZero_i <= '1';
else
CoarseZero_i <= '0';
end if;
end process;
CZeroDly(N-4 downto 0) <= (others => '0');
CZeroDly(N-4 downto 0) <= (others => '0');
Disabled <= (not Enabled) or ( CoarseZero_i);
Disabled <= (not Enabled) or ( CoarseZero_i);
visual_B_CoarseDly_sub_tmp_a <= (CoarseDly_i(N-4 downto 0));
visual_B_CoarseDly_sub_tmp_b <= (COne(N-4 downto 0));
visual_B_CoarseDly_sub_dif_int <= std_logic_vector((unsigned('0' &
visual_B_CoarseDly_sub_tmp_a)
- unsigned('0' & visual_B_CoarseDly_sub_tmp_b)));
visual_B_CoarseDly_sub_tmp_a <= (CoarseDly_i(N-4 downto 0));
visual_B_CoarseDly_sub_tmp_b <= (COne(N-4 downto 0));
visual_B_CoarseDly_sub_dif_int <= std_logic_vector((unsigned('0' &
visual_B_CoarseDly_sub_tmp_a) - unsigned('0' & visual_B_CoarseDly_sub_tmp_b)));
CoarseDly(N-4 downto 0) <= (visual_B_CoarseDly_sub_dif_int((N-4) - (0) +
1 - 1 downto 0));
CoarseDly(N-4 downto 0) <= visual_B_CoarseDly_sub_dif_int((N-4) + 1 - 1 downto 0);
COne(N-4 downto 0) <= (0=>'1', others=>'0');
SyncPulse_i <= ((not RemoveDoubleSync) or (not Sync_prev)) and (( Sync_i));
SyncPulse_i <= ((not RemoveDoubleSync) or (not Sync_prev)) and Sync_i;
ClearOutGoodNext <= (not UseNextValue) or ( Disabled) or ( OutGoodNext);
ClearOutGoodNext <= (not UseNextValue) or Disabled or OutGoodNext;
OutputEnabled_i <= ( OutMuxSel) and (not Disabled);
OutputEnabled_i <= OutMuxSel and (not Disabled);
CoarseZero <= CoarseZero_i;
......
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