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wr2rf-vme
Commits
60809b52
Commit
60809b52
authored
Apr 23, 2020
by
Tristan Gingold
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vtuCore: simplify HDL, remove wvalue_effective.
parent
ecbb265e
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103 deletions
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-103
vtuCore.vhd
dependencies/vtu/rtl/vtuCore.vhd
+12
-103
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dependencies/vtu/rtl/vtuCore.vhd
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60809b52
...
...
@@ -816,77 +816,6 @@ begin
end
process
vtuSeq_Idle
;
end
vtuSeq
;
----------------------------------------------------
--
-- Library Name : CommonVisual
-- Unit Name : LimSubtrN
-- Unit Type : Text Unit
--
------------------------------------------------------
--------------------------------------------------------------------
--------------------------------------------------------------------
-- Date : Thu Oct 22 15:44:29 2009
--
-- Author : Gregoire Hagmann
--
-- Company : CERN BE/RF/FB
--
-- Description : Subtractor with signed data bus and limiter circuitry
--
--------------------------------------------------------------------
--------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
library
ieee
;
use
ieee
.
NUMERIC_STD
.
all
;
entity
LimSubtrN
is
port
(
A
:
in
std_logic_vector
;
--vector size defined by the signals connected to the block
B
:
in
std_logic_vector
;
lim
:
out
std_logic
;
O
:
out
std_logic_vector
);
end
;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- Date : Thu Oct 22 15:44:29 2009
--
-- Author : Gregoire Hagmann
--
-- Company : CERN BE/RF/FB
--
-- Description : Subtractor with signed data bus and limiter circuitry
--
--------------------------------------------------------------------
--------------------------------------------------------------------
architecture
V1
of
LimSubtrN
is
signal
l_sum
:
std_logic_vector
(
O
'length
downto
0
):
=
(
others
=>
'0'
);
--default value for simulation only
constant
c_ValMax
:
std_logic_vector
(
O
'range
):
=
(
'0'
,
others
=>
'1'
);
constant
c_ValMin
:
std_logic_vector
(
O
'range
):
=
(
'1'
,
others
=>
'0'
);
begin
process
(
l_sum
)
begin
if
l_sum
(
O
'length
)
=
'0'
and
l_sum
(
O
'length
-1
)
=
'1'
then
--Val max positive
O
<=
c_ValMax
;
Lim
<=
'1'
;
elsif
l_sum
(
O
'length
)
=
'1'
and
l_sum
(
O
'length
-1
)
=
'0'
then
--Val max negative
O
<=
c_ValMin
;
Lim
<=
'1'
;
else
O
<=
l_sum
(
O
'length
-1
downto
0
);
Lim
<=
'0'
;
end
if
;
end
process
;
l_sum
<=
std_logic_vector
(
resize
(
signed
(
A
),
O
'length
+
1
)
-
resize
(
signed
(
B
),
O
'length
+
1
));
end
;
----------------------------------------------------
--
...
...
@@ -1222,7 +1151,7 @@ architecture vtuCore of vtuCore is
signal
wrongValue
:
std_logic
;
signal
SyncLessEna
:
std_logic
;
signal
DataOutLowFreq
:
std_logic_vector
(
7
downto
0
);
signal
DataIn_
2
:
std_logic_vector
(
7
downto
0
);
signal
DataIn_
HT
:
std_logic_vector
(
7
downto
0
);
signal
Shifter2Ena
:
std_logic
;
signal
DataInHTSyncLess
:
std_logic_vector
(
7
downto
0
);
signal
wValueOne_seq
:
std_logic
;
...
...
@@ -1235,7 +1164,6 @@ architecture vtuCore of vtuCore is
signal
counterEnable
:
std_logic
;
signal
DataOutPlayMem
:
std_logic_vector
(
7
downto
0
);
signal
SwitchtoHT
:
std_logic
;
signal
wValue_effective
:
std_logic_vector
(
63
downto
0
);
signal
Shifter1Ena
:
std_logic
;
signal
DataOut_HT
:
std_logic_vector
(
7
downto
0
);
signal
HTSwitchEna
:
std_logic
;
...
...
@@ -1318,16 +1246,10 @@ begin
OutputEnabled
=>
OE_HT
,
Clk
=>
Clk
,
Delay
=>
htValue_effective
,
DataIn
=>
DataIn_
2
,
DataIn
=>
DataIn_
HT
,
Enabled
=>
Shifter2Ena
,
SyncPulse
=>
open
);
B_LimSubtr
:
entity
work
.
LimSubtrN
port
map
(
A
=>
wValue
(
63
downto
0
),
B
=>
COne
(
63
downto
0
),
lim
=>
open
,
O
=>
wValue_effective
(
63
downto
0
));
B_vtuSeq
:
entity
work
.
vtuSeq
port
map
(
Clk
=>
Clk
,
Rst
=>
Rst
,
...
...
@@ -1462,10 +1384,10 @@ begin
case
SwitchtoHT
is
when
'0'
=>
-- B datashifter to HT datashifter
DataIn_
2
<=
DataOut_B
;
DataIn_
HT
<=
DataOut_B
;
when
others
=>
-- HT datashifter loopback.
DataIn_
2
<=
DataOut_HT
;
DataIn_
HT
<=
DataOut_HT
;
end
case
;
end
process
;
...
...
@@ -1508,39 +1430,26 @@ begin
begin
if
Clk
'event
and
Clk
=
'1'
then
if
counterReset
=
'1'
then
PulseCount
<=
(
others
=>
'0'
);
-- Start at 1 so that WindowDone_seq is set for the next pulse.
PulseCount
<=
x"0000_0000_0000_0001"
;
elsif
counterEnable
=
'1'
then
PulseCount
<=
std_logic_vector
(
unsigned
(
PulseCount
)
+
1
);
end
if
;
end
if
;
end
process
;
process
(
PulseCount
,
wValue
_effective
)
process
(
PulseCount
,
wValue
)
begin
if
InfiniteWindow
=
'1'
or
(
unsigned
(
PulseCount
)
<
unsigned
(
wValue_effective
))
then
WindowDone_seq
<=
'0'
;
else
if
InfiniteWindow
=
'0'
and
(
unsigned
(
PulseCount
)
>=
unsigned
(
wValue
))
then
WindowDone_seq
<=
'1'
;
else
WindowDone_seq
<=
'0'
;
end
if
;
end
process
;
process
(
wValue_effective
)
begin
if
wValue_effective
=
(
63
downto
0
=>
'0'
)
then
wValueOne
<=
'1'
;
else
wValueOne
<=
'0'
;
end
if
;
end
process
;
wValueOne
<=
'1'
when
wValue
=
x"0000_0000_0000_0001"
else
'0'
;
process
(
wValue
)
begin
if
wValue
=
(
63
downto
0
=>
'0'
)
then
wValueZero
<=
'1'
;
else
wValueZero
<=
'0'
;
end
if
;
end
process
;
wValueZero
<=
'1'
when
wValue
=
x"0000_0000_0000_0000"
else
'0'
;
wValueOne_seq
<=
(
wValueOne
or
SinglePulseMode
)
and
(
not
InfiniteWindow
);
...
...
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