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wr2rf-vme
Commit 686b9948 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: top level now allows the WRCore to access flash memory

parent 5ec4d9eb
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Showing with 7 additions and 6 deletions
hdl/top/wr2rf_vme/wr2rf_vme.vhd
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...@@ -529,6 +529,7 @@ architecture rtl of wr2rf_vme is ...@@ -529,6 +529,7 @@ architecture rtl of wr2rf_vme is
signal ila_clk : std_logic; signal ila_clk : std_logic;
signal ila_sigs : std_logic_vector(127 downto 0); signal ila_sigs : std_logic_vector(127 downto 0);
signal dbg : std_logic_vector(15 downto 0); signal dbg : std_logic_vector(15 downto 0);
signal spi_flash_cs_n_sys : std_logic; signal spi_flash_cs_n_sys : std_logic;
signal spi_flash_mosi_sys : std_logic; signal spi_flash_mosi_sys : std_logic;
signal spi_flash_sck_sys : std_logic; signal spi_flash_sck_sys : std_logic;
...@@ -681,6 +682,7 @@ begin ...@@ -681,6 +682,7 @@ begin
g_with_external_clock_input => true, g_with_external_clock_input => true,
-- --
g_board_name => "WRRF", g_board_name => "WRRF",
g_ram_address_space_size_kb => 256,
g_phys_uart => true, g_phys_uart => true,
g_virtual_uart => true, g_virtual_uart => true,
g_aux_clks => 0, g_aux_clks => 0,
...@@ -696,7 +698,6 @@ begin ...@@ -696,7 +698,6 @@ begin
g_softpll_use_sampled_ref_clocks => true, g_softpll_use_sampled_ref_clocks => true,
g_vuart_fifo_size => 1024 ) g_vuart_fifo_size => 1024 )
port map( port map(
dbg_o => dbg,
clk_sys_i => clk_sys_62m5, clk_sys_i => clk_sys_62m5,
clk_dmtd_i => clk_dmtd_62m5, clk_dmtd_i => clk_dmtd_62m5,
clk_ref_i => clk_sys_62m5, --clk_125m_ref, clk_ref_i => clk_sys_62m5, --clk_125m_ref,
...@@ -744,7 +745,7 @@ begin ...@@ -744,7 +745,7 @@ begin
spi_sclk_o => spi_flash_sck_wrc, spi_sclk_o => spi_flash_sck_wrc,
spi_ncs_o => spi_flash_cs_n_wrc, spi_ncs_o => spi_flash_cs_n_wrc,
spi_mosi_o => spi_flash_mosi_wrc, spi_mosi_o => spi_flash_mosi_wrc,
spi_miso_i => flash_miso_i, spi_miso_i => spi_flash_miso_i,
uart_rxd_i => '1', uart_rxd_i => '1',
uart_txd_o => open, uart_txd_o => open,
owr_pwren_o => open, owr_pwren_o => open,
...@@ -1343,9 +1344,9 @@ begin ...@@ -1343,9 +1344,9 @@ begin
ila0 => ila_sigs ); ila0 => ila_sigs );
flash_cs_n_o <= flash_cs_n_sys and flash_cs_n_wrc; spi_flash_cs_n_o <= spi_flash_cs_n_sys and spi_flash_cs_n_wrc;
flash_mosi_o <= flash_mosi_sys or flash_mosi_wrc; spi_flash_mosi_o <= spi_flash_mosi_sys or spi_flash_mosi_wrc;
flash_sck <= flash_sck_sys or flash_sck_wrc; spi_flash_sck <= spi_flash_sck_sys or spi_flash_sck_wrc;
STARTUPE2_inst : STARTUPE2 STARTUPE2_inst : STARTUPE2
generic map ( generic map (
...@@ -1362,7 +1363,7 @@ begin ...@@ -1362,7 +1363,7 @@ begin
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name) GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => flash_sck, -- 1-bit input: User CCLK input USRCCLKO => spi_flash_sck, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '0', -- 1-bit input: User DONE pin output control USRDONEO => '0', -- 1-bit input: User DONE pin output control
USRDONETS => '1' -- 1-bit input: User DONE 3-state enable output USRDONETS => '1' -- 1-bit input: User DONE 3-state enable output
......
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