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wr2rf-vme
Commits
751ae006
Commit
751ae006
authored
May 19, 2020
by
Tristan Gingold
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Plain Diff
Add fw flash interface, connect eeprom to wr core.
parent
e60eddee
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4 changed files
with
109 additions
and
37 deletions
+109
-37
wr2rf_core.vhd
hdl/rtl/wr2rf_core.vhd
+30
-9
wr2rf_init_regs.cheby
hdl/rtl/wr2rf_init_regs.cheby
+7
-0
wr2rf_vme_regs.vhd
hdl/rtl/wr2rf_vme_regs.vhd
+46
-2
wr2rf_vme.vhd
hdl/top/wr2rf_vme.vhd
+26
-26
No files found.
hdl/rtl/wr2rf_core.vhd
View file @
751ae006
...
...
@@ -89,7 +89,11 @@ entity wr2rf_core is
rf2_t2_delay_oen_o
:
out
std_logic
;
rf2_t2_mux_sel_o
:
out
std_logic
;
rf_delay_o
:
out
std_logic_vector
(
9
downto
0
)
rf_delay_o
:
out
std_logic_vector
(
9
downto
0
);
flash_cs_n_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
);
end
;
...
...
@@ -106,6 +110,9 @@ architecture arch of wr2rf_core is
signal
wrpc_wb16_in
:
t_wishbone_master_in
;
signal
wrpc_wb16_out
:
t_wishbone_master_out
;
signal
fw_update_in
:
t_wishbone_master_in
;
signal
fw_update_out
:
t_wishbone_master_out
;
signal
rf1_t1_delay_data
,
rf1_t2_delay_data
,
rf2_t1_delay_data
,
rf2_t2_delay_data
:
std_logic_vector
(
15
downto
0
);
signal
rf1_t1_delay_wr
,
rf1_t2_delay_wr
,
rf2_t1_delay_wr
,
rf2_t2_delay_wr
:
std_logic
;
begin
...
...
@@ -135,6 +142,9 @@ begin
init_rf_spi_i
=>
rf_spi_in
,
init_rf_spi_o
=>
rf_spi_out
,
init_fw_update_i
=>
fw_update_in
,
init_fw_update_o
=>
fw_update_out
,
init_rf_i
=>
rf_in
,
init_rf_o
=>
rf_out
,
...
...
@@ -236,12 +246,23 @@ begin
end
process
;
inst_wb16x32
:
entity
work
.
wb16_to_wb32
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
wb16_i
=>
wrpc_wb16_out
,
wb16_o
=>
wrpc_wb16_in
,
wb32_i
=>
wrc_wb_i
,
wb32_o
=>
wrc_wb_o
);
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
wb16_i
=>
wrpc_wb16_out
,
wb16_o
=>
wrpc_wb16_in
,
wb32_i
=>
wrc_wb_i
,
wb32_o
=>
wrc_wb_o
);
inst_wb_fw_update
:
entity
work
.
xwb_xc7_fw_update
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
wb_i
=>
fw_update_out
,
wb_o
=>
fw_update_in
,
flash_cs_n_o
=>
flash_cs_n_o
,
flash_mosi_o
=>
flash_mosi_o
,
flash_miso_i
=>
flash_miso_i
);
end
arch
;
hdl/rtl/wr2rf_init_regs.cheby
View file @
751ae006
...
...
@@ -62,6 +62,13 @@ memory-map:
cs1: IQ DAC 1
cs2: IQ DAC 2
filename: oc_spi16_regs.cheby
- submap:
name: fw_update
description: Firmware update (FAR)
size: 0x02
interface: wb-16
x-hdl:
busgroup: True
# TODO: interrupt controller.
- submap:
name: rf
...
...
hdl/rtl/wr2rf_vme_regs.vhd
View file @
751ae006
...
...
@@ -61,6 +61,10 @@ entity wr2rf_vme_regs is
init_rf_spi_i
:
in
t_wishbone_master_in
;
init_rf_spi_o
:
out
t_wishbone_master_out
;
-- Firmware update (FAR)
init_fw_update_i
:
in
t_wishbone_master_in
;
init_fw_update_o
:
out
t_wishbone_master_out
;
-- Register for RF components
init_rf_i
:
in
t_wishbone_master_in
;
init_rf_o
:
out
t_wishbone_master_out
;
...
...
@@ -125,6 +129,13 @@ architecture syn of wr2rf_vme_regs is
signal
init_rf_spi_tr
:
std_logic
;
signal
init_rf_spi_wack
:
std_logic
;
signal
init_rf_spi_rack
:
std_logic
;
signal
init_fw_update_re
:
std_logic
;
signal
init_fw_update_we
:
std_logic
;
signal
init_fw_update_wt
:
std_logic
;
signal
init_fw_update_rt
:
std_logic
;
signal
init_fw_update_tr
:
std_logic
;
signal
init_fw_update_wack
:
std_logic
;
signal
init_fw_update_rack
:
std_logic
;
signal
init_rf_re
:
std_logic
;
signal
init_rf_we
:
std_logic
;
signal
init_rf_wt
:
std_logic
;
...
...
@@ -362,6 +373,28 @@ begin
init_rf_spi_o
.
we
<=
init_rf_spi_wt
;
init_rf_spi_o
.
dat
(
15
downto
0
)
<=
wr_dat_d0
;
-- Interface init_fw_update
init_fw_update_tr
<=
init_fw_update_wt
or
init_fw_update_rt
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
init_fw_update_rt
<=
'0'
;
init_fw_update_wt
<=
'0'
;
else
init_fw_update_rt
<=
(
init_fw_update_rt
or
init_fw_update_re
)
and
not
init_fw_update_rack
;
init_fw_update_wt
<=
(
init_fw_update_wt
or
init_fw_update_we
)
and
not
init_fw_update_wack
;
end
if
;
end
if
;
end
process
;
init_fw_update_o
.
cyc
<=
init_fw_update_tr
;
init_fw_update_o
.
stb
<=
init_fw_update_tr
;
init_fw_update_wack
<=
init_fw_update_i
.
ack
and
init_fw_update_wt
;
init_fw_update_rack
<=
init_fw_update_i
.
ack
and
init_fw_update_rt
;
init_fw_update_o
.
adr
<=
((
30
downto
0
=>
'0'
)
&
adr_int
(
0
downto
1
))
&
(
0
downto
0
=>
'0'
);
init_fw_update_o
.
sel
(
1
downto
0
)
<=
wr_sel_d0
;
init_fw_update_o
.
we
<=
init_fw_update_wt
;
init_fw_update_o
.
dat
(
15
downto
0
)
<=
wr_dat_d0
;
-- Interface init_rf
init_rf_tr
<=
init_rf_wt
or
init_rf_rt
;
process
(
clk_i
)
begin
...
...
@@ -407,7 +440,7 @@ begin
init_wrpc_o
.
dat
(
15
downto
0
)
<=
wr_dat_d0
;
-- Process for write requests.
process
(
wr_adr_d0
,
wr_req_d0
,
ctrl_rf1_vtus_wack
,
ctrl_rf2_vtus_wack
,
ctrl_reg1_wack
,
ctrl_reg2_wack
,
init_clock_ctrl_wack
,
init_tmg_wack
,
init_pll_spi_wack
,
init_rf_spi_wack
,
init_rf_wack
,
init_wrpc_wack
)
begin
process
(
wr_adr_d0
,
wr_req_d0
,
ctrl_rf1_vtus_wack
,
ctrl_rf2_vtus_wack
,
ctrl_reg1_wack
,
ctrl_reg2_wack
,
init_clock_ctrl_wack
,
init_tmg_wack
,
init_pll_spi_wack
,
init_rf_spi_wack
,
init_
fw_update_wack
,
init_
rf_wack
,
init_wrpc_wack
)
begin
ctrl_rf1_vtus_we
<=
'0'
;
ctrl_rf2_vtus_we
<=
'0'
;
ctrl_reg1_wreq
<=
'0'
;
...
...
@@ -416,6 +449,7 @@ begin
init_tmg_wreq
<=
'0'
;
init_pll_spi_we
<=
'0'
;
init_rf_spi_we
<=
'0'
;
init_fw_update_we
<=
'0'
;
init_rf_we
<=
'0'
;
init_wrpc_we
<=
'0'
;
case
wr_adr_d0
(
18
downto
17
)
is
...
...
@@ -472,6 +506,10 @@ begin
init_rf_spi_we
<=
wr_req_d0
;
wr_ack_int
<=
init_rf_spi_wack
;
when
"000000000011"
=>
-- Submap init_fw_update
init_fw_update_we
<=
wr_req_d0
;
wr_ack_int
<=
init_fw_update_wack
;
when
"000000000100"
=>
-- Submap init_rf
init_rf_we
<=
wr_req_d0
;
wr_ack_int
<=
init_rf_wack
;
...
...
@@ -488,13 +526,14 @@ begin
end
process
;
-- Process for read requests.
process
(
adr_int
,
rd_req_int
,
ctrl_rf1_vtus_i
.
dat
,
ctrl_rf1_vtus_rack
,
ctrl_rf2_vtus_i
.
dat
,
ctrl_rf2_vtus_rack
,
ctrl_reg1_reg
,
ctrl_reg2_reg
,
init_clock_ctrl_clk_sel_reg
,
init_clock_ctrl_mmcm_reset_reg
,
init_clock_status_mmcm_locked_i
,
init_tmg_io_term_reg
,
init_tmg_clk_term_reg
,
init_tmg_clk_oe_reg
,
init_tmg_io_dir_reg
,
init_pll_spi_i
.
dat
,
init_pll_spi_rack
,
init_rf_spi_i
.
dat
,
init_rf_spi_rack
,
init_rf_i
.
dat
,
init_rf_rack
,
init_wrpc_i
.
dat
,
init_wrpc_rack
)
begin
process
(
adr_int
,
rd_req_int
,
ctrl_rf1_vtus_i
.
dat
,
ctrl_rf1_vtus_rack
,
ctrl_rf2_vtus_i
.
dat
,
ctrl_rf2_vtus_rack
,
ctrl_reg1_reg
,
ctrl_reg2_reg
,
init_clock_ctrl_clk_sel_reg
,
init_clock_ctrl_mmcm_reset_reg
,
init_clock_status_mmcm_locked_i
,
init_tmg_io_term_reg
,
init_tmg_clk_term_reg
,
init_tmg_clk_oe_reg
,
init_tmg_io_dir_reg
,
init_pll_spi_i
.
dat
,
init_pll_spi_rack
,
init_rf_spi_i
.
dat
,
init_rf_spi_rack
,
init_
fw_update_i
.
dat
,
init_fw_update_rack
,
init_
rf_i
.
dat
,
init_rf_rack
,
init_wrpc_i
.
dat
,
init_wrpc_rack
)
begin
-- By default ack read requests
rd_dat_d0
<=
(
others
=>
'X'
);
ctrl_rf1_vtus_re
<=
'0'
;
ctrl_rf2_vtus_re
<=
'0'
;
init_pll_spi_re
<=
'0'
;
init_rf_spi_re
<=
'0'
;
init_fw_update_re
<=
'0'
;
init_rf_re
<=
'0'
;
init_wrpc_re
<=
'0'
;
case
adr_int
(
18
downto
17
)
is
...
...
@@ -564,6 +603,11 @@ begin
rd_dat_d0
<=
init_rf_spi_i
.
dat
(
15
downto
0
);
rd_ack_d0
<=
init_rf_spi_rack
;
when
"000000000011"
=>
-- Submap init_fw_update
init_fw_update_re
<=
rd_req_int
;
rd_dat_d0
<=
init_fw_update_i
.
dat
(
15
downto
0
);
rd_ack_d0
<=
init_fw_update_rack
;
when
"000000000100"
=>
-- Submap init_rf
init_rf_re
<=
rd_req_int
;
rd_dat_d0
<=
init_rf_i
.
dat
(
15
downto
0
);
...
...
hdl/top/wr2rf_vme.vhd
View file @
751ae006
...
...
@@ -132,11 +132,15 @@ entity wr2rf_vme is
wr_dac_ocxo_din_o
:
out
std_logic
;
wr_dac_ocxo_cs_n_o
:
out
std_logic
;
-- Flash
-- F
irmware f
lash
spi_flash_cs_n_o
:
out
std_logic
;
spi_flash_miso_i
:
in
std_logic
;
spi_flash_mosi_o
:
out
std_logic
;
-- WR eeprom
wr_eeprom_scl_b
:
inout
std_logic
;
wr_eeprom_sda_b
:
inout
std_logic
;
-- Onewire
wr_onewire_b
:
inout
std_logic
;
...
...
@@ -327,7 +331,10 @@ architecture rtl of wr2rf_vme is
signal
sfp1_sda_out
:
std_logic
;
signal
sfp1_sda_in
:
std_logic
;
signal
spi_flash_clk
:
std_logic
;
signal
wr1_scl_out
:
std_logic
;
signal
wr1_scl_in
:
std_logic
;
signal
wr1_sda_out
:
std_logic
;
signal
wr1_sda_in
:
std_logic
;
signal
owr_en
:
std_logic_vector
(
1
downto
0
);
signal
owr_i
:
std_logic_vector
(
1
downto
0
);
...
...
@@ -539,15 +546,19 @@ begin
phy_sfp_tx_disable_o
=>
open
,
--sfp0_tx,
led_act_o
=>
sfp1_led_active_o
,
led_link_o
=>
sfp1_led_link_o
,
scl_o
=>
wr1_scl_out
,
scl_i
=>
wr1_scl_in
,
sda_o
=>
wr1_sda_out
,
sda_i
=>
wr1_sda_in
,
sfp_scl_o
=>
sfp1_scl_out
,
sfp_scl_i
=>
sfp1_scl_in
,
sfp_sda_o
=>
sfp1_sda_out
,
sfp_sda_i
=>
sfp1_sda_in
,
sfp_det_i
=>
sfp1_detect_i
,
spi_sclk_o
=>
spi_flash_clk
,
spi_ncs_o
=>
spi_flash_cs_n_o
,
spi_mosi_o
=>
spi_flash_mosi_o
,
spi_miso_i
=>
spi_flash_miso_i
,
spi_sclk_o
=>
open
,
spi_ncs_o
=>
open
,
spi_mosi_o
=>
open
,
spi_miso_i
=>
'1'
,
uart_rxd_i
=>
'1'
,
uart_txd_o
=>
open
,
owr_pwren_o
=>
open
,
...
...
@@ -628,6 +639,11 @@ begin
owr_i
(
0
)
<=
wr_onewire_b
;
owr_i
(
1
)
<=
'1'
;
wr_eeprom_scl_b
<=
'0'
when
wr1_scl_out
=
'0'
else
'Z'
;
wr_eeprom_sda_b
<=
'0'
when
wr1_sda_out
=
'0'
else
'Z'
;
wr1_scl_in
<=
wr_eeprom_scl_b
;
wr1_sda_in
<=
wr_eeprom_sda_b
;
process
(
clk_sys_62m5
)
begin
if
rising_edge
(
clk_sys_62m5
)
then
...
...
@@ -635,25 +651,6 @@ begin
end
if
;
end
process
;
inst_Kintex7_Startup
:
STARTUPE2
generic
map
(
PROG_USR
=>
"FALSE"
,
SIM_CCLK_FREQ
=>
0
.
0
)
port
map
(
CFGCLK
=>
open
,
CFGMCLK
=>
open
,
EOS
=>
open
,
PREQ
=>
open
,
CLK
=>
'0'
,
GSR
=>
'0'
,
GTS
=>
'0'
,
KEYCLEARB
=>
'1'
,
PACK
=>
'1'
,
USRCCLKO
=>
spi_flash_clk
,
USRCCLKTS
=>
'0'
,
-- always out
USRDONEO
=>
'1'
,
USRDONETS
=>
'1'
);
-----------------------------------------------------------------------------
-- VME64x Core and buffers
-----------------------------------------------------------------------------
...
...
@@ -899,8 +896,11 @@ begin
rf2_t2_delay_oen_o
=>
rf2_t2_delay_oen_o
,
rf2_t2_mux_sel_o
=>
rf2_t2_mux_sel_o
,
rf_delay_o
=>
rf_delay_o
rf_delay_o
=>
rf_delay_o
,
flash_cs_n_o
=>
spi_flash_cs_n_o
,
flash_miso_i
=>
spi_flash_miso_i
,
flash_mosi_o
=>
spi_flash_mosi_o
);
-- timing_io
...
...
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