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wr2rf-vme
Commit 7542cfa9 authored by John Gill's avatar John Gill
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Added option to build for sfp1, cleaned timing, registers to control trigger… 

Added option to build for sfp1, cleaned timing, registers to control trigger unit pulse shaper output and delay control +++
parent 154c28c1
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Showing with 649 additions and 362 deletions
RFNCO @ 1bdaf345
Subproject commit 98658724acee445ac455a5935cadbc54c5f34d41
Subproject commit 1bdaf34592a5871b3b2769e84dcc764a56f8bf88
hdl/rtl/Manifest.py
View file @ 7542cfa9
......@@ -3,6 +3,7 @@ files = ['vtu_blk.vhd',
'../../dependencies/vtu/rtl/vtuCore.vhd',
'xwb_spi16.vhd',
'wr2rf_sysclks.vhd',
'wr2rf_extclk.vhd',
'wr2rf_rftrigger.vhd',
'wr2rf_vme_p0.vhd',
'wr2rf_regs_core.vhd',
......
hdl/rtl/registers/trigunit_regs.vhd
View file @ 7542cfa9
-- Do not edit. Generated on Tue Jan 26 11:31:28 2021 by tgingold
-- Do not edit. Generated on Thu Feb 04 16:02:46 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/registers/wr2rf_init_regs.cheby
View file @ 7542cfa9
......@@ -109,6 +109,10 @@ memory-map:
name: clk_oe
description: independent bidirectional control for clock outputs
range: 11-10
- field:
name: test_mode
description: drive tmg_clk and tmg_io with test output signal
range: 15
- reg:
name: tmg_io_rf1
description: timing io grouping of signals
......
hdl/rtl/registers/wr2rf_init_rf_ch_regs.cheby
View file @ 7542cfa9
......@@ -34,10 +34,14 @@ memory-map:
range: 0
- field:
name: mux_sel
description: Select between the delayed output (=0) or the delayed and shaped output (=1)
range: 1
- reg:
name: delay
access: wo
width: 16
x-hdl:
write-strobe: True
- field:
name: trig_rst
range: 2
preset: 1
- field:
name: delay_latch
description: A 0->1 transition latches the rf_trigger_delay value
range: 3
preset: 1
\ No newline at end of file
hdl/rtl/registers/wr2rf_init_rf_regs.cheby
View file @ 7542cfa9
......@@ -5,6 +5,11 @@ memory-map:
x-hdl:
busgroup: True
children:
- reg:
name: rf_trigger_delay
description: Sets the rf trigger unit delay value
access: rw
width: 16
- submap:
name: rf1
filename: wr2rf_init_rf_ch_regs.cheby
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ 7542cfa9
This diff is collapsed.
hdl/rtl/registers/wr2rf_rfnco_regs.vhd
View file @ 7542cfa9
-- Do not edit. Generated on Tue Jan 26 11:31:29 2021 by tgingold
-- Do not edit. Generated on Thu Feb 04 16:02:48 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i RFNCO.cheby --gen-hdl
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ 7542cfa9
-- Do not edit. Generated on Tue Jan 26 11:31:29 2021 by tgingold
-- Do not edit. Generated on Thu Feb 04 16:02:47 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ 7542cfa9
-- Do not edit. Generated on Tue Jan 26 11:31:30 2021 by tgingold
-- Do not edit. Generated on Thu Feb 04 16:02:48 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......@@ -78,6 +78,8 @@ entity wr2rf_vme_regs is
init_tmg_clk_term_o : out std_logic_vector(1 downto 0);
-- independent bidirectional control for clock outputs
init_tmg_clk_oe_o : out std_logic_vector(1 downto 0);
-- drive tmg_clk and tmg_io with test output signal
init_tmg_test_mode_o : out std_logic;
-- timing io grouping of signals
-- Select between rfx_frevs and rf_sync for tmg_io(3)
......@@ -372,6 +374,7 @@ architecture syn of wr2rf_vme_regs is
signal init_tmg_io_oe_reg : std_logic_vector(3 downto 0);
signal init_tmg_clk_term_reg : std_logic_vector(1 downto 0);
signal init_tmg_clk_oe_reg : std_logic_vector(1 downto 0);
signal init_tmg_test_mode_reg : std_logic;
signal init_tmg_wreq : std_logic;
signal init_tmg_wack : std_logic;
signal init_tmg_io_rf1_sel_reg : std_logic;
......@@ -793,6 +796,7 @@ begin
init_tmg_io_oe_o <= init_tmg_io_oe_reg;
init_tmg_clk_term_o <= init_tmg_clk_term_reg;
init_tmg_clk_oe_o <= init_tmg_clk_oe_reg;
init_tmg_test_mode_o <= init_tmg_test_mode_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
......@@ -800,6 +804,7 @@ begin
init_tmg_io_oe_reg <= "0000";
init_tmg_clk_term_reg <= "00";
init_tmg_clk_oe_reg <= "00";
init_tmg_test_mode_reg <= '0';
init_tmg_wack <= '0';
else
if init_tmg_wreq = '1' then
......@@ -807,6 +812,7 @@ begin
init_tmg_io_oe_reg <= wr_dat_d0(7 downto 4);
init_tmg_clk_term_reg <= wr_dat_d0(9 downto 8);
init_tmg_clk_oe_reg <= wr_dat_d0(11 downto 10);
init_tmg_test_mode_reg <= wr_dat_d0(15);
end if;
init_tmg_wack <= init_tmg_wreq;
end if;
......@@ -2888,7 +2894,7 @@ begin
end process;
-- Process for read requests.
process (adr_int, rd_req_int, init_hwinfo_serialNumber_i, init_hwinfo_ident_cardID_i, init_hwinfo_ident_extendedID_i, init_hwinfo_ident_jtagRemoteDisable_i, init_hwinfo_firmwareVersion_i, init_hwinfo_memMapVersion_i, init_hwinfo_echo_echo_reg, init_fw_update_i.dat, init_fw_update_rack, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_wrcore_ctrl_reset_n_reg, init_iodelay_ctrl_reset_reg, init_clock_status_mmcm_locked_i, init_clock_status_shift_busy_i, init_tmg_io_term_reg, init_tmg_io_oe_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_tmg_io_rf1_sel_reg, init_tmg_io_rf2_sel_reg, init_tmg_frev_rf1_sel_reg, init_tmg_frev_rf2_sel_reg, init_pin_ctrl_ext_ref_dir_reg, init_pll_status_error_i, init_pll_status_locked_i, init_pll_ctrl_sync_reg, init_dds_ctrl_reset_reg, init_dds_ctrl_profile_reg, init_dds_status_sync_error_i, init_ocxo_ctrl_enable_reg, init_ocxo_uptime_val_i, init_nco_azimuthal_value_reg, init_nco_cabledelay_value_reg, init_nco_hb_value_reg, init_nco_h1_ftw_value_reg, init_nco_h1_prog_value_reg, init_nco_ctrl_reset_nco_reg, init_nco_ctrl_reset_slip_reg, init_nco_ctrl_reset_fsk_reg, init_nco_ctrl_rate_reg, init_nco_loc_or_wrs_params_sel_reg, init_svec_mup_ctrl_gpio_sel_reg, init_svec_mup_ctrl_led_sel_reg, init_svec_mup_ctrl_bclk_rfclk_sel_reg, init_svec_mup_ctrl_ila_sel_reg, init_svec_mup_rftrig_t1stop_reg, init_svec_mup_rftrig_t1start_reg, init_svec_mup_rftrig_t2stop_reg, init_svec_mup_rftrig_t2start_reg, init_svec_mup_fmc1_term_reg, init_svec_mup_fmc1_oe_n_reg, init_svec_mup_fmc1_led_reg, init_svec_mup_fmc2_term_reg, init_svec_mup_fmc2_oe_n_reg, init_svec_mup_fmc2_led_reg, init_wrs_rxframe_ftw_value_i, init_wrs_rxframe_ctrl_i, init_wrs_rxframe_counter_i, init_wrc_tai_value_i, init_wrc_cycles_value_i, init_wrc_status_linkup_i, init_wrc_status_time_valid_i, init_wrc_page0_reg, init_wrc_page1_reg, init_txframe_ftw_h1_main_reg, init_txframe_ftw_h1_prog_reg, init_txframe_ftw_h1_on_reg, init_txframe_dftw_h1_slip1_reg, init_txframe_dftw_h1_slip2_reg, init_txframe_setpoint1_reg, init_txframe_setpoint2_reg, init_txframe_setpoint3_reg, init_txframe_setpoint4_reg, init_txframe_setpoint5_reg, init_txframe_setpoint6_reg, init_txframe_setpoint7_reg, init_txframe_setpoint8_reg, init_txframe_noise_reg, init_txframe_control_reg, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_rf_i.dat, init_rf_rack, init_framerxtx_i.dat, init_framerxtx_rack, init_wrpc_i.dat, init_wrpc_rack, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_rf1_rfnco_i.dat, ctrl_rf1_rfnco_rack, ctrl_rf2_rfnco_i.dat, ctrl_rf2_rfnco_rack, ctrl_rf1_iqdac_igain_reg, ctrl_rf1_iqdac_qgain_reg, ctrl_rf2_iqdac_igain_reg, ctrl_rf2_iqdac_qgain_reg, ctrl_rf1_iqdac_ctrl_reg, ctrl_rf2_iqdac_ctrl_reg, ctrl_iqdac_ram_addr_reg, ctrl_iqdac_ram_data_reg, ctrl_iqdac_ram_write_reg, ctrl_iqdac_ram_play_reg, ctrl_rf1_dds_ftw_valid_reg, ctrl_rf1_dds_ftw_reg, ctrl_rf2_dds_ftw_valid_reg, ctrl_rf2_dds_ftw_reg) begin
process (adr_int, rd_req_int, init_hwinfo_serialNumber_i, init_hwinfo_ident_cardID_i, init_hwinfo_ident_extendedID_i, init_hwinfo_ident_jtagRemoteDisable_i, init_hwinfo_firmwareVersion_i, init_hwinfo_memMapVersion_i, init_hwinfo_echo_echo_reg, init_fw_update_i.dat, init_fw_update_rack, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_wrcore_ctrl_reset_n_reg, init_iodelay_ctrl_reset_reg, init_clock_status_mmcm_locked_i, init_clock_status_shift_busy_i, init_tmg_io_term_reg, init_tmg_io_oe_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_tmg_test_mode_reg, init_tmg_io_rf1_sel_reg, init_tmg_io_rf2_sel_reg, init_tmg_frev_rf1_sel_reg, init_tmg_frev_rf2_sel_reg, init_pin_ctrl_ext_ref_dir_reg, init_pll_status_error_i, init_pll_status_locked_i, init_pll_ctrl_sync_reg, init_dds_ctrl_reset_reg, init_dds_ctrl_profile_reg, init_dds_status_sync_error_i, init_ocxo_ctrl_enable_reg, init_ocxo_uptime_val_i, init_nco_azimuthal_value_reg, init_nco_cabledelay_value_reg, init_nco_hb_value_reg, init_nco_h1_ftw_value_reg, init_nco_h1_prog_value_reg, init_nco_ctrl_reset_nco_reg, init_nco_ctrl_reset_slip_reg, init_nco_ctrl_reset_fsk_reg, init_nco_ctrl_rate_reg, init_nco_loc_or_wrs_params_sel_reg, init_svec_mup_ctrl_gpio_sel_reg, init_svec_mup_ctrl_led_sel_reg, init_svec_mup_ctrl_bclk_rfclk_sel_reg, init_svec_mup_ctrl_ila_sel_reg, init_svec_mup_rftrig_t1stop_reg, init_svec_mup_rftrig_t1start_reg, init_svec_mup_rftrig_t2stop_reg, init_svec_mup_rftrig_t2start_reg, init_svec_mup_fmc1_term_reg, init_svec_mup_fmc1_oe_n_reg, init_svec_mup_fmc1_led_reg, init_svec_mup_fmc2_term_reg, init_svec_mup_fmc2_oe_n_reg, init_svec_mup_fmc2_led_reg, init_wrs_rxframe_ftw_value_i, init_wrs_rxframe_ctrl_i, init_wrs_rxframe_counter_i, init_wrc_tai_value_i, init_wrc_cycles_value_i, init_wrc_status_linkup_i, init_wrc_status_time_valid_i, init_wrc_page0_reg, init_wrc_page1_reg, init_txframe_ftw_h1_main_reg, init_txframe_ftw_h1_prog_reg, init_txframe_ftw_h1_on_reg, init_txframe_dftw_h1_slip1_reg, init_txframe_dftw_h1_slip2_reg, init_txframe_setpoint1_reg, init_txframe_setpoint2_reg, init_txframe_setpoint3_reg, init_txframe_setpoint4_reg, init_txframe_setpoint5_reg, init_txframe_setpoint6_reg, init_txframe_setpoint7_reg, init_txframe_setpoint8_reg, init_txframe_noise_reg, init_txframe_control_reg, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_rf_i.dat, init_rf_rack, init_framerxtx_i.dat, init_framerxtx_rack, init_wrpc_i.dat, init_wrpc_rack, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_rf1_rfnco_i.dat, ctrl_rf1_rfnco_rack, ctrl_rf2_rfnco_i.dat, ctrl_rf2_rfnco_rack, ctrl_rf1_iqdac_igain_reg, ctrl_rf1_iqdac_qgain_reg, ctrl_rf2_iqdac_igain_reg, ctrl_rf2_iqdac_qgain_reg, ctrl_rf1_iqdac_ctrl_reg, ctrl_rf2_iqdac_ctrl_reg, ctrl_iqdac_ram_addr_reg, ctrl_iqdac_ram_data_reg, ctrl_iqdac_ram_write_reg, ctrl_iqdac_ram_play_reg, ctrl_rf1_dds_ftw_valid_reg, ctrl_rf1_dds_ftw_reg, ctrl_rf2_dds_ftw_valid_reg, ctrl_rf2_dds_ftw_reg) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
init_fw_update_re <= '0';
......@@ -3026,7 +3032,8 @@ begin
rd_dat_d0(7 downto 4) <= init_tmg_io_oe_reg;
rd_dat_d0(9 downto 8) <= init_tmg_clk_term_reg;
rd_dat_d0(11 downto 10) <= init_tmg_clk_oe_reg;
rd_dat_d0(15 downto 12) <= (others => '0');
rd_dat_d0(14 downto 12) <= (others => '0');
rd_dat_d0(15) <= init_tmg_test_mode_reg;
when "01000" =>
-- Reg init_tmg_io_rf1
rd_ack_d0 <= rd_req_int;
......
hdl/rtl/vtu_blk.vhd
View file @ 7542cfa9
......@@ -55,6 +55,7 @@ entity vtu_blk is
trig_o : out std_logic;
-- dff reset (pad)
trig_rst_i : in std_logic;
trig_rst_n_o : out std_logic;
trig_rst_p_o : out std_logic;
......@@ -588,7 +589,7 @@ begin
generic map (
IOSTANDARD => "LVDS" )
port map (
I => '0', -- FIXME
I => trig_rst_i,
O => trig_rst_p_o,
OB => trig_rst_n_o );
end rtl;
hdl/rtl/wr2rf_extclk.vhd 0 → 100644
View file @ 7542cfa9
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
--
-- https://www.ohwr.org/projects/wr2rf-vme
--------------------------------------------------------------------------------
--
-- unit name: wr2rf_sysclks
--
-- description: Provides clean clocks for further distribution and usage
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity wr2rf_extclk is
port (
clk_ext_10m_i : in std_logic;
clk_ext_stopped_o : out std_logic;
clk_ext_reset_i : in std_logic;
clk_ext_locked_o : out std_logic;
clk_ext_125m_o : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of wr2rf_extclk : entity is "yes";
end entity;
architecture rtl of wr2rf_extclk is
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
begin
mmcm_adv_inst : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 62.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 5.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 100.000,
REF_JITTER1 => 0.010)
port map (
-- Output clocks
CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clk_ext_10m_i,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => clk_ext_locked_o,
CLKINSTOPPED => clk_ext_stopped_o,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => clk_ext_reset_i );
clkf_buf : BUFG
port map (
O => clkfbout_buf,
I => clkfbout );
clkout1_buf : BUFG
port map (
O => clk_ext_125m_o,
I => clkout0 );
end architecture;
hdl/rtl/wr2rf_regs_core.vhd
View file @ 7542cfa9
......@@ -104,8 +104,9 @@ entity wr2rf_regs_core is
tmg_io_term_en_o : out std_logic_vector(4 downto 1);
tmg_clk_oe_o : out std_logic_vector(1 downto 0);
tmg_io_oe_o : out std_logic_vector(4 downto 1);
tmg_test_mode_o : out std_logic;
tmg_io_rf1_sel_o : out std_logic;
tmg_io_rf2_sel_o : out std_logic;
tmg_io_rf2_sel_o : out std_logic;
tmg_frev_rf1_sel_o : out std_logic;
tmg_frev_rf2_sel_o : out std_logic;
ext_ref_dir_o : out std_logic;
......@@ -171,25 +172,33 @@ entity wr2rf_regs_core is
rf1_mixer_en_o : out std_logic;
rf1_iqdac_reset_o : out std_logic;
rf1_t1_delay_latch_o : out std_logic;
rf1_t1_delay_oen_o : out std_logic;
rf1_t1_mux_sel_o : out std_logic;
rf1_t2_delay_latch_o : out std_logic;
rf1_t1_rst_o : out std_logic;
rf1_t1_delay_latch_o : out std_logic;
rf1_t2_delay_oen_o : out std_logic;
rf1_t2_mux_sel_o : out std_logic;
rf1_t2_rst_o : out std_logic;
rf1_t2_delay_latch_o : out std_logic;
-- RF 2
rf2_mux_sel_o : out std_logic_vector(1 downto 0);
rf2_mixer_en_o : out std_logic;
rf2_iqdac_reset_o : out std_logic;
rf2_t1_delay_latch_o : out std_logic;
rf2_iqdac_reset_o : out std_logic;
rf2_t1_delay_oen_o : out std_logic;
rf2_t1_mux_sel_o : out std_logic;
rf2_t2_delay_latch_o : out std_logic;
rf2_t1_rst_o : out std_logic;
rf2_t1_delay_latch_o : out std_logic;
rf2_t2_delay_oen_o : out std_logic;
rf2_t2_mux_sel_o : out std_logic;
rf_delay_o : out std_logic_vector(9 downto 0);
rf2_t2_rst_o : out std_logic;
rf2_t2_delay_latch_o : out std_logic;
rf_trig_delay_o : out std_logic_vector(9 downto 0);
flash_cs_n_o : out std_logic;
flash_mosi_o : out std_logic;
......@@ -255,6 +264,7 @@ architecture arch of wr2rf_regs_core is
signal rf1_t2_delay_wr : std_logic;
signal rf2_t1_delay_wr : std_logic;
signal rf2_t2_delay_wr : std_logic;
signal rf_trigger_delay : std_logic_vector(15 downto 0);
signal rf1_dds_ftw_valid : std_logic_vector(15 downto 0);
signal rf1_dds_ftw : std_logic_vector(63 downto 0);
......@@ -263,7 +273,7 @@ architecture arch of wr2rf_regs_core is
signal wrc_page_0, wrc_page_1, wrc_page : std_logic_vector(31 downto 0);
signal txframe_payload : t_RFmFramePayload;
signal txframe_payload_r : t_RFmFramePayload;
signal txframe_payload_r : t_RFmFramePayload;
signal txframe_ftw_h1_main : std_logic_vector(63 downto 0);
signal txframe_ftw_h1_prog : std_logic_vector(63 downto 0);
signal txframe_ftw_h1_on : std_logic_vector(63 downto 0);
......@@ -285,7 +295,7 @@ architecture arch of wr2rf_regs_core is
attribute keep_hierarchy of inst_wr2rf_regs : label is "yes";
attribute shreg_extract of inst_wr2rf_regs : label is "no";
begin
inst_wr2rf_regs: entity work.wr2rf_vme_regs
......@@ -302,7 +312,7 @@ begin
init_hwinfo_firmwareVersion_i => x"0001_00_00",
init_hwinfo_memMapVersion_i => x"0001_00_00",
init_hwinfo_echo_echo_o => open,
init_fw_update_i => wb_fw_update_in,
init_fw_update_o => wb_fw_update_out,
......@@ -324,8 +334,9 @@ begin
init_tmg_clk_term_o => tmg_clk_term_en_o,
init_tmg_clk_oe_o => tmg_clk_oe_o,
init_tmg_io_oe_o => tmg_io_oe_o,
init_tmg_test_mode_o => tmg_test_mode_o,
init_tmg_io_rf1_sel_o => tmg_io_rf1_sel_o,
init_tmg_io_rf2_sel_o => tmg_io_rf2_sel_o,
init_tmg_io_rf2_sel_o => tmg_io_rf2_sel_o,
init_tmg_frev_rf1_sel_o => tmg_frev_rf1_sel_o,
init_tmg_frev_rf2_sel_o => tmg_frev_rf2_sel_o,
......@@ -471,8 +482,8 @@ begin
end process;
txframe_payload_o <= txframe_payload_r;
inst_rf_spi: entity work.xwb_spi16
generic map (
......@@ -514,55 +525,57 @@ begin
pad_miso_i => pll_main_sdo_i
);
my_inst: entity work.wr2rf_init_rf_regs
my_inst: entity work.wr2rf_init_rf_regs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_i => wb_rf_out,
wb_o => wb_rf_in,
rf1_common_mixer_en_o => rf1_mixer_en_o,
rf1_common_mux_sel_o => rf1_mux_sel_o,
rf1_common_iqdac_reset_o => rf1_iqdac_reset_o,
rf1_ch_0_csr_delay_oen_o => rf1_t1_delay_oen_o,
rf1_ch_0_csr_mux_sel_o => rf1_t1_mux_sel_o,
rf1_ch_0_delay_o => rf1_t1_delay_data,
rf1_ch_0_delay_wr_o => rf1_t1_delay_wr,
rf1_ch_1_csr_delay_oen_o => rf1_t2_delay_oen_o,
rf1_ch_1_csr_mux_sel_o => rf1_t2_mux_sel_o,
rf1_ch_1_delay_o => rf1_t2_delay_data,
rf1_ch_1_delay_wr_o => rf1_t2_delay_wr,
rf2_common_mixer_en_o => rf2_mixer_en_o,
rf2_common_mux_sel_o => rf2_mux_sel_o,
rf2_common_iqdac_reset_o => rf2_iqdac_reset_o,
rf2_ch_0_csr_delay_oen_o => rf2_t1_delay_oen_o,
rf2_ch_0_csr_mux_sel_o => rf2_t1_mux_sel_o,
rf2_ch_0_delay_o => rf2_t1_delay_data,
rf2_ch_0_delay_wr_o => rf2_t1_delay_wr,
rf2_ch_1_csr_delay_oen_o => rf2_t2_delay_oen_o,
rf2_ch_1_csr_mux_sel_o => rf2_t2_mux_sel_o,
rf2_ch_1_delay_o => rf2_t2_delay_data,
rf2_ch_1_delay_wr_o => rf2_t2_delay_wr );
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rf1_t1_delay_wr = '1' then
rf_delay_o <= rf1_t1_delay_data(9 downto 0);
elsif rf1_t2_delay_wr = '1' then
rf_delay_o <= rf1_t2_delay_data(9 downto 0);
elsif rf1_t2_delay_wr = '1' then
rf_delay_o <= rf2_t1_delay_data(9 downto 0);
elsif rf1_t2_delay_wr = '1' then
rf_delay_o <= rf2_t2_delay_data(9 downto 0);
else
rf_delay_o <= (others => '0');
end if;
rf1_t1_delay_latch_o <= rf1_t1_delay_wr;
rf1_t2_delay_latch_o <= rf1_t2_delay_wr;
rf2_t1_delay_latch_o <= rf2_t1_delay_wr;
rf2_t2_delay_latch_o <= rf2_t2_delay_wr;
end if;
end process;
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_i => wb_rf_out,
wb_o => wb_rf_in,
rf_trigger_delay_o => rf_trigger_delay,
rf1_common_mixer_en_o => rf1_mixer_en_o,
rf1_common_mux_sel_o => rf1_mux_sel_o,
rf1_common_iqdac_reset_o => rf1_iqdac_reset_o,
rf1_ch_0_csr_delay_oen_o => rf1_t1_delay_oen_o,
rf1_ch_0_csr_mux_sel_o => rf1_t1_mux_sel_o,
rf1_ch_0_csr_trig_rst_o => rf1_t1_rst_o,
rf1_ch_0_csr_delay_latch_o => rf1_t1_delay_latch_o,
rf1_ch_1_csr_delay_oen_o => rf1_t2_delay_oen_o,
rf1_ch_1_csr_mux_sel_o => rf1_t2_mux_sel_o,
rf1_ch_1_csr_trig_rst_o => rf1_t2_rst_o,
rf1_ch_1_csr_delay_latch_o => rf1_t2_delay_latch_o,
rf2_common_mixer_en_o => rf2_mixer_en_o,
rf2_common_mux_sel_o => rf2_mux_sel_o,
rf2_common_iqdac_reset_o => rf2_iqdac_reset_o,
rf2_ch_0_csr_delay_oen_o => rf2_t1_delay_oen_o,
rf2_ch_0_csr_mux_sel_o => rf2_t1_mux_sel_o,
rf2_ch_0_csr_trig_rst_o => rf2_t1_rst_o,
rf2_ch_0_csr_delay_latch_o => rf2_t1_delay_latch_o,
rf2_ch_1_csr_delay_oen_o => rf2_t2_delay_oen_o,
rf2_ch_1_csr_mux_sel_o => rf2_t2_mux_sel_o,
rf2_ch_1_csr_trig_rst_o => rf2_t2_rst_o,
rf2_ch_1_csr_delay_latch_o => rf2_t2_delay_latch_o );
rf_trig_delay_o <= rf_trigger_delay(9 downto 0);
--process(clk_sys_i)
--begin
-- if rising_edge(clk_sys_i) then
-- if rf1_t1_delay_wr = '1' then
-- rf_delay_o <= rf1_t1_delay_data(9 downto 0);
-- elsif rf1_t2_delay_wr = '1' then
-- rf_delay_o <= rf1_t2_delay_data(9 downto 0);
-- elsif rf1_t2_delay_wr = '1' then
-- rf_delay_o <= rf2_t1_delay_data(9 downto 0);
-- elsif rf1_t2_delay_wr = '1' then
-- rf_delay_o <= rf2_t2_delay_data(9 downto 0);
-- else
-- rf_delay_o <= (others => '0');
-- end if;
-- rf1_t1_delay_latch_o <= rf1_t1_delay_wr;
-- rf1_t2_delay_latch_o <= rf1_t2_delay_wr;
-- rf2_t1_delay_latch_o <= rf2_t1_delay_wr;
-- rf2_t2_delay_latch_o <= rf2_t2_delay_wr;
-- end if;
--end process;
inst_wrc_wb16x32: entity work.wb16_to_wb32
port map (
......
hdl/rtl/wr2rf_rftrigger.vhd
View file @ 7542cfa9
......@@ -56,6 +56,7 @@ entity wr2rf_rftrigger is
rf_t1_clk_n_i : in std_logic;
rf_t1_p_o : inout std_logic;
rf_t1_n_o : inout std_logic;
rf_t1_rst_i : in std_logic;
rf_t1_rst_p_o : out std_logic;
rf_t1_rst_n_o : out std_logic;
rf_t1_start_i : in std_logic; -- Asynchronous tmg inputs.
......@@ -65,6 +66,7 @@ entity wr2rf_rftrigger is
rf_t2_clk_n_i : in std_logic;
rf_t2_p_o : inout std_logic;
rf_t2_n_o : inout std_logic;
rf_t2_rst_i : in std_logic;
rf_t2_rst_p_o : out std_logic;
rf_t2_rst_n_o : out std_logic;
rf_t2_start_i : in std_logic; -- Asynchronous tmg inputs.
......@@ -184,6 +186,7 @@ begin
clk_vtu_i => clk_vtu,
sync_i => rf_sync,
trig_o => rf_t1_out,
trig_rst_i => rf_t1_rst_i,
trig_rst_p_o => rf_t1_rst_p_o,
trig_rst_n_o => rf_t1_rst_n_o,
start_i => rf_t1_start_i,
......@@ -221,6 +224,7 @@ begin
clk_vtu_i => clk_vtu,
sync_i => rf_t1_fb,
trig_o => rf_t2_out,
trig_rst_i => rf_t2_rst_i,
trig_rst_p_o => rf_t2_rst_p_o,
trig_rst_n_o => rf_t2_rst_n_o,
start_i => rf_t2_start_i,
......
hdl/syn/wr2rf_vme/wr2rf_dmtd_falsepath.tcl 0 → 100644
View file @ 7542cfa9
set endcells [get_cells -hier -filter {name=~*clk_i_d0_reg && file_name=~*dmtd_sampler.vhd}]
# DEBUG
foreach endcell [get_cells $endcells] {
puts $endcell
}
#return
foreach endcell [get_cells $endcells] {
set_false_path -to $endcell
}
hdl/syn/wr2rf_vme/wr2rf_vme.tcl
View file @ 7542cfa9
......@@ -18,12 +18,13 @@ if {![file exists files.tcl]} {
source files.tcl
#read_edif ../../top/wr2rf_vme/debug/dds_compiler_v5_0.ngc;
#add_files -norecurse ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd;
#set_property IS_GLOBAL_INCLUDE 1 [get_files ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd];
#set_property LIBRARY work [get_files ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd];
# constraint files
set swap_sfp false
if {$swap_sfp eq "true"} {
read_xdc $projDir/${top}_sfp_swap.xdc
} else {
read_xdc $projDir/${top}_sfp.xdc
}
read_xdc $projDir/${top}.xdc
set start_time [clock seconds]
......@@ -34,6 +35,7 @@ write_checkpoint -force ${top}_synth
source wr2rf_async_regs.tcl
source wr2rf_maxdelays.tcl
source wr2rf_dmtd_falsepath.tcl
#opt_design -directive Explore -verbose > ${top}_opt.log
#write_checkpoint -force ${top}_opt
......@@ -58,7 +60,8 @@ report_io -file ${top}_pin.rpt
# bitstream configuration...
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]
set_property CONFIG_MODE SPIx1 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
# CONFIGRATE valid values for 7 series: 3, 6, 9, 12, 16, 22, 26, 33, 40, 50, 66
set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
......
hdl/syn/wr2rf_vme/wr2rf_vme.xdc
View file @ 7542cfa9
This diff is collapsed.
hdl/syn/wr2rf_vme/wr2rf_vme_sfp.xdc 0 → 100644
View file @ 7542cfa9
set_property PACKAGE_PIN G4 [get_ports sfp1_rx_p_i]
set_property PACKAGE_PIN F2 [get_ports sfp1_tx_p_o]
#set_property PACKAGE_PIN E4 [get_ports sfp2_rx_p_i]
#set_property PACKAGE_PIN D2 [get_ports sfp2_tx_p_o]
set_property PACKAGE_PIN H9 [get_ports sfp1_detect_i];#D8
set_property PACKAGE_PIN J8 [get_ports sfp1_los_i];#D9
set_property PACKAGE_PIN F9 [get_ports sfp1_rate_select_o];#F8
set_property PACKAGE_PIN H11 [get_ports sfp1_scl_b];#F9
set_property PACKAGE_PIN G9 [get_ports sfp1_sda_b];#H11
set_property PACKAGE_PIN F8 [get_ports sfp1_tx_fault_i];#A9
set_property PACKAGE_PIN G10 [get_ports sfp1_tx_disable_o];#A8
set_property PACKAGE_PIN J10 [get_ports sfp1_led_link_o];#C9
set_property PACKAGE_PIN H8 [get_ports sfp1_led_active_o];#B9
set_property PACKAGE_PIN D9 [get_ports sfp2_detect_i];#G9
set_property PACKAGE_PIN H12 [get_ports sfp2_los_i];#G10
set_property PACKAGE_PIN D8 [get_ports sfp2_rate_select_o];#H8
set_property PACKAGE_PIN G12 [get_ports sfp2_scl_b];#H9
set_property PACKAGE_PIN D11 [get_ports sfp2_sda_b];#J8
set_property PACKAGE_PIN C14 [get_ports sfp2_tx_disable_o];#E11
set_property PACKAGE_PIN E12 [get_ports sfp2_tx_fault_i];#J13
set_property PACKAGE_PIN H13 [get_ports sfp2_led_link_o];#J11
set_property PACKAGE_PIN C9 [get_ports sfp2_led_active_o];#J10
hdl/syn/wr2rf_vme/wr2rf_vme_sfp_swap.xdc 0 → 100644
View file @ 7542cfa9
#set_property PACKAGE_PIN G4 [get_ports sfp2_rx_p_i]
#set_property PACKAGE_PIN F2 [get_ports sfp2_tx_p_o]
set_property PACKAGE_PIN E4 [get_ports sfp1_rx_p_i]
set_property PACKAGE_PIN D2 [get_ports sfp1_tx_p_o]
set_property PACKAGE_PIN H9 [get_ports sfp2_detect_i];#D8
set_property PACKAGE_PIN J8 [get_ports sfp2_los_i];#D9
set_property PACKAGE_PIN F9 [get_ports sfp2_rate_select_o];#F8
set_property PACKAGE_PIN H11 [get_ports sfp2_scl_b];#F9
set_property PACKAGE_PIN G9 [get_ports sfp2_sda_b];#H11
set_property PACKAGE_PIN F8 [get_ports sfp2_tx_fault_i];#A9
set_property PACKAGE_PIN G10 [get_ports sfp2_tx_disable_o];#A8
set_property PACKAGE_PIN J10 [get_ports sfp2_led_link_o];#C9
set_property PACKAGE_PIN H8 [get_ports sfp2_led_active_o];#B9
set_property PACKAGE_PIN D9 [get_ports sfp1_detect_i];#G9
set_property PACKAGE_PIN H12 [get_ports sfp1_los_i];#G10
set_property PACKAGE_PIN D8 [get_ports sfp1_rate_select_o];#H8
set_property PACKAGE_PIN G12 [get_ports sfp1_scl_b];#H9
set_property PACKAGE_PIN D11 [get_ports sfp1_sda_b];#J8
set_property PACKAGE_PIN C14 [get_ports sfp1_tx_disable_o];#E11
set_property PACKAGE_PIN E12 [get_ports sfp1_tx_fault_i];#J13
set_property PACKAGE_PIN H13 [get_ports sfp1_led_link_o];#J11
set_property PACKAGE_PIN C9 [get_ports sfp1_led_active_o];#J10
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 7542cfa9
This diff is collapsed.
software/include/wr2rf_init_regs.h
View file @ 7542cfa9
#ifndef __CHEBY__WR2RF_INIT_REGS__H__
#define __CHEBY__WR2RF_INIT_REGS__H__
#include "wr2rf_init_rf_regs.h"
#include "oc_spi16_regs.h"
#include "hwInfo.h"
#include "wr2rf_init_rf_regs.h"
#define WR2RF_INIT_REGS_SIZE 16384 /* 0x4000 = 16KB */
/* RF indentification */
......@@ -49,6 +49,7 @@
#define WR2RF_INIT_REGS_TMG_CLK_TERM_SHIFT 8
#define WR2RF_INIT_REGS_TMG_CLK_OE_MASK 0xc00UL
#define WR2RF_INIT_REGS_TMG_CLK_OE_SHIFT 10
#define WR2RF_INIT_REGS_TMG_TEST_MODE 0x8000UL
/* timing io grouping of signals */
#define WR2RF_INIT_REGS_TMG_IO_RF1 0x110UL
......@@ -534,7 +535,7 @@ cs2: IQ DAC 2
struct wr2rf_init_rf_regs rf;
/* padding to: 192 words */
uint32_t __padding_6[8];
uint32_t __padding_6[10];
/* [0x300]: SUBMAP RF Frame transceiver */
uint32_t framerxtx[16];
......
software/include/wr2rf_init_rf_ch_regs.h
View file @ 7542cfa9
#ifndef __CHEBY__WR2RF_INIT_RF_CH_REGS__H__
#define __CHEBY__WR2RF_INIT_RF_CH_REGS__H__
#define WR2RF_INIT_RF_CH_REGS_SIZE 16 /* 0x10 */
#define WR2RF_INIT_RF_CH_REGS_SIZE 8 /* 0x8 */
/* Control register for both channels */
#define WR2RF_INIT_RF_CH_REGS_COMMON 0x0UL
......@@ -10,31 +10,27 @@
#define WR2RF_INIT_RF_CH_REGS_COMMON_IQDAC_RESET 0x8UL
/* None */
#define WR2RF_INIT_RF_CH_REGS_CH 0x8UL
#define WR2RF_INIT_RF_CH_REGS_CH_SIZE 4 /* 0x4 */
#define WR2RF_INIT_RF_CH_REGS_CH 0x4UL
#define WR2RF_INIT_RF_CH_REGS_CH_SIZE 2 /* 0x2 */
/* None */
#define WR2RF_INIT_RF_CH_REGS_CH_CSR 0x0UL
#define WR2RF_INIT_RF_CH_REGS_CH_CSR_DELAY_OEN 0x1UL
#define WR2RF_INIT_RF_CH_REGS_CH_CSR_MUX_SEL 0x2UL
/* None */
#define WR2RF_INIT_RF_CH_REGS_CH_DELAY 0x2UL
#define WR2RF_INIT_RF_CH_REGS_CH_CSR_TRIG_RST 0x4UL
#define WR2RF_INIT_RF_CH_REGS_CH_CSR_DELAY_LATCH 0x8UL
struct wr2rf_init_rf_ch_regs {
/* [0x0]: REG (rw) Control register for both channels */
uint16_t common;
/* padding to: 8 words */
uint8_t __padding_0[6];
/* padding to: 4 words */
uint8_t __padding_0[2];
/* [0x8]: REPEAT (no description) */
/* [0x4]: REPEAT (no description) */
struct ch {
/* [0x0]: REG (rw) (no description) */
uint16_t csr;
/* [0x2]: REG (wo) (no description) */
uint16_t delay;
} ch[2];
};
......
software/include/wr2rf_init_rf_regs.h
View file @ 7542cfa9
......@@ -2,18 +2,27 @@
#define __CHEBY__WR2RF_INIT_RF_REGS__H__
#include "wr2rf_init_rf_ch_regs.h"
#define WR2RF_INIT_RF_REGS_SIZE 32 /* 0x20 */
#define WR2RF_INIT_RF_REGS_SIZE 24 /* 0x18 */
/* Sets the rf trigger unit delay value */
#define WR2RF_INIT_RF_REGS_RF_TRIGGER_DELAY 0x0UL
/* None */
#define WR2RF_INIT_RF_REGS_RF1 0x0UL
#define WR2RF_INIT_RF_REGS_RF1_SIZE 16 /* 0x10 */
#define WR2RF_INIT_RF_REGS_RF1 0x8UL
#define WR2RF_INIT_RF_REGS_RF1_SIZE 8 /* 0x8 */
/* None */
#define WR2RF_INIT_RF_REGS_RF2 0x10UL
#define WR2RF_INIT_RF_REGS_RF2_SIZE 16 /* 0x10 */
#define WR2RF_INIT_RF_REGS_RF2_SIZE 8 /* 0x8 */
struct wr2rf_init_rf_regs {
/* [0x0]: SUBMAP (no description) */
/* [0x0]: REG (rw) Sets the rf trigger unit delay value */
uint16_t rf_trigger_delay;
/* padding to: 8 words */
uint8_t __padding_0[6];
/* [0x8]: SUBMAP (no description) */
struct wr2rf_init_rf_ch_regs rf1;
/* [0x10]: SUBMAP (no description) */
......
software/include/wr2rf_rfnco_regs.h
View file @ 7542cfa9
......@@ -3,8 +3,8 @@
#include "ipInfo.h"
#define RFNCO_SIZE 4096 /* 0x1000 = 4KB */
#define RFNCO_MEMMAP_VERSION 0x1UL
#define RFNCO_IDENT 0xffUL
#define RFNCO_MEMMAP_VERSION 0x10000UL
#define RFNCO_IDENT 0x14UL
/* None */
#define RFNCO_IPINFO 0x0UL
......
software/include/wr2rf_vme_regs.h
View file @ 7542cfa9
#ifndef __CHEBY__WR2RF_VME_REGS__H__
#define __CHEBY__WR2RF_VME_REGS__H__
#include "wr2rf_init_regs.h"
#include "wr2rf_ctrl_regs.h"
#include "wr2rf_init_regs.h"
#define WR2RF_VME_REGS_SIZE 32768 /* 0x8000 = 32KB */
/* Memory map for the initialization part */
......
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