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wr2rf-vme
Commit 9224773d authored by John Robert Gill's avatar John Robert Gill
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merge

parents c7c6cf52 4f8ea3f9
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Showing with 285 additions and 145 deletions
hdl/rtl/vtu_blk.vhd
View file @ 9224773d
......@@ -235,7 +235,7 @@ begin
process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_sys_n = '0' then
if rst_sys_n = '0' or rst_vtu_n = '0' then
start_pulse_2 <= '0';
miss_ready <= '0';
miss_valid <= '0';
......@@ -258,20 +258,11 @@ begin
miss_valid <= not valid_offline;
end if;
end if;
if start_ack = '1' then
-- Copy for online registers.
-- Clear valid
valid_offline <= '0';
elsif valid_wr = '1' then
-- Write to VALID register from WB.
-- TODO: do not allow change of offline data if the valid bit is set.
-- TODO: detect ingored writes to offline data if the valid bit is set.
valid_offline <= valid_data;
end if;
end if;
end if;
end process;
-- Handle start pulse to vtu
process (clk_vtu_i)
begin
if rising_edge (clk_vtu_i) then
......@@ -300,6 +291,27 @@ begin
end if;
end process;
-- Handle offline valid bit
process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_sys_n = '0' then
valid_offline <= '0';
else
if start_ack = '1' and not rst_vtu_n = '0' then
-- Copy for online registers.
-- Clear valid
valid_offline <= '0';
elsif valid_wr = '1' then
-- Write to VALID register from WB.
-- TODO: do not allow change of offline data if the valid bit is set.
-- TODO: detect ignored writes to offline data if the valid bit is set.
valid_offline <= valid_data;
end if;
end if;
end if;
end process;
-- VTU status synchronizers
inst_run_sync: entity work.gc_sync
port map (
......@@ -470,7 +482,7 @@ begin
inst_vtu : entity work.vtuCore
port map (
-- Interface to the memory for the play memory mode.
-- Interface to the memory for the play memory mode (not used).
Mem_RdDone => '1',
Mem_Addr => open,
Mem_RdData => x"00",
......
hdl/rtl/vtu_diag.vhd
View file @ 9224773d
......@@ -96,6 +96,9 @@ architecture arch of vtu_diag is
signal freq_wr : std_logic;
signal dat_d : std_logic_vector(8 downto 0);
signal rst_sig_n : std_logic;
begin
assert g_CLK_FREQ mod 2000 = 0
report "inaccurate results due to clk frequency"
......@@ -193,10 +196,19 @@ begin
d_p_i => gate_pulse,
q_p_o => gate_pulse_synced);
-- resync reset from clk to the sig domain
inst_sig_rst_sync : entity work.gc_sync
port map (
clk_i => sig_i,
rst_n_a_i => '1',
d_i => rst_n_i,
q_o => rst_sig_n );
inst_sig_sync : entity work.gc_sync
port map (
clk_i => sig_i,
rst_n_a_i => rst_n_i,
rst_n_a_i => rst_sig_n,
d_i => enable_i,
q_o => enable_sig);
......
hdl/rtl/wr2rf_regs_core.vhd
View file @ 9224773d
......@@ -204,6 +204,11 @@ entity wr2rf_regs_core is
ila_sigs_o : out std_logic_vector(7 downto 0) );
attribute keep_hierarchy : string;
attribute shreg_extract : string;
attribute keep_hierarchy of wr2rf_regs_core : entity is "yes";
attribute shreg_extract of wr2rf_regs_core : entity is "no";
end;
architecture arch of wr2rf_regs_core is
......@@ -255,7 +260,8 @@ architecture arch of wr2rf_regs_core is
signal rf2_dds_ftw : std_logic_vector(63 downto 0);
signal wrc_page_0, wrc_page_1, wrc_page : std_logic_vector(31 downto 0);
signal txframe_payload : t_RFmFramePayload;
signal txframe_payload_r : t_RFmFramePayload;
signal txframe_ftw_h1_main : std_logic_vector(63 downto 0);
signal txframe_ftw_h1_prog : std_logic_vector(63 downto 0);
signal txframe_ftw_h1_on : std_logic_vector(63 downto 0);
......@@ -271,6 +277,11 @@ architecture arch of wr2rf_regs_core is
signal txframe_setpoint8 : std_logic_vector(31 downto 0);
signal txframe_noise : std_logic_vector(31 downto 0);
signal txframe_control : std_logic_vector(15 downto 0);
attribute keep_hierarchy of inst_wr2rf_regs : label is "yes";
attribute shreg_extract of inst_wr2rf_regs : label is "no";
begin
inst_wr2rf_regs: entity work.wr2rf_vme_regs
......@@ -422,7 +433,7 @@ begin
rf2_dds_ftw_valid_o <= rf2_dds_ftw_valid(0);
rf2_dds_ftw_o <= rf2_dds_ftw(47 downto 0);
txframe_payload_o <= (
txframe_payload <= (
FTW_H1_main => txframe_ftw_h1_main(47 downto 0),
FTW_H1_prog => txframe_ftw_h1_prog(47 downto 0),
FTW_H1_on => txframe_ftw_h1_on(47 downto 0),
......@@ -439,6 +450,17 @@ begin
noise => txframe_noise,
control => txframe_control);
process (clk_sys_i) is
begin
if rising_edge(clk_sys_i) then
txframe_payload_r <= txframe_payload;
end if;
end process;
txframe_payload_o <= txframe_payload_r;
inst_rf_spi: entity work.xwb_spi16
generic map (
g_interface_mode => CLASSIC,
......
hdl/rtl/wr2rf_rfchan.vhd
View file @ 9224773d
This diff is collapsed.
hdl/rtl/wr2rf_rftrigger.vhd
View file @ 9224773d
......@@ -76,6 +76,8 @@ entity wr2rf_rftrigger is
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of wr2rf_rftrigger : entity is "yes";
attribute shreg_extract : STRING;
attribute shreg_extract of wr2rf_rftrigger : entity is "no";
end entity;
......@@ -155,8 +157,13 @@ begin
I => rf_sync_i);
ila_dbg_o(0) <= rf_clk_in;
ila_dbg_o(1) <= rf_sync;
ila_dbg_o(7 downto 2) <= (others => '0');
ila_dbg_o(1) <= '0';
ila_dbg_o(2) <= rf_t1_start_i;
ila_dbg_o(3) <= rf_t1_stop_i;
ila_dbg_o(4) <= '0';
ila_dbg_o(5) <= rf_t2_start_i;
ila_dbg_o(6) <= rf_t2_stop_i;
ila_dbg_o(7) <= '0';
process (clk_sys_i)
begin
......@@ -164,7 +171,7 @@ begin
rst_sys_r <= rst_sys_i;
rst_sys_n_r <= rst_sys_n_i;
end if;
end process;
end process;
rf_t1_i : entity work.vtu_blk
port map (
......
hdl/syn/wr2rf_vme/wr2rf_vme.tcl
View file @ 9224773d
......@@ -18,10 +18,10 @@ if {![file exists files.tcl]} {
source files.tcl
read_edif ../../top/wr2rf_vme/debug/dds_compiler_v5_0.ngc;
add_files -norecurse ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd;
set_property IS_GLOBAL_INCLUDE 1 [get_files ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd];
set_property LIBRARY work [get_files ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd];
#read_edif ../../top/wr2rf_vme/debug/dds_compiler_v5_0.ngc;
#add_files -norecurse ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd;
#set_property IS_GLOBAL_INCLUDE 1 [get_files ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd];
#set_property LIBRARY work [get_files ../../top/wr2rf_vme/debug/dds_compiler_v5_0.vhd];
# constraint files
read_xdc $projDir/${top}.xdc
......
hdl/syn/wr2rf_vme/wr2rf_vme.xdc
View file @ 9224773d
......@@ -1462,9 +1462,13 @@ set_false_path -to [get_cells inst_rf2_trigger/rf_t1_i/inst_ISERDESE2]
set_false_path -to [get_cells inst_rf2_trigger/rf_t2_i/inst_ISERDESE2]
###################################
# Idelayctrls for RF banks
###################################
set_property LOC IDELAYCTRL_X1Y2 [get_cells inst_rf1_trigger/rf_IDELAYCTRL]
set_property LOC IDELAYCTRL_X1Y0 [get_cells inst_rf2_trigger/rf_IDELAYCTRL]
###################################
# Debug < o > dont look
###################################
set_false_path -to [get_cells ila_i/ila0_r_reg[*]]
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 9224773d
......@@ -301,6 +301,11 @@ entity wr2rf_vme is
rf_delay_o : out std_logic_vector(9 downto 0) );
attribute keep_hierarchy : string;
attribute shreg_extract : string;
attribute keep_hierarchy of wr2rf_vme : entity is "yes";
attribute shreg_extract of wr2rf_vme : entity is "no";
end wr2rf_vme;
architecture rtl of wr2rf_vme is
......@@ -430,6 +435,7 @@ architecture rtl of wr2rf_vme is
signal tmg_clk_oe_o : std_logic_vector(2 downto 1);
signal tmg_io_oe_o : std_logic_vector(4 downto 1);
signal tmg_io : std_logic_vector(4 downto 3);
signal tmg_io_rf1_sel : std_logic;
signal tmg_io_rf2_sel : std_logic;
signal tmg_frev_rf1_sel : std_logic;
......@@ -559,8 +565,14 @@ architecture rtl of wr2rf_vme is
signal rft1_ila_dbg : std_logic_vector(7 downto 0);
signal rft2_ila_dbg : std_logic_vector(7 downto 0);
signal vme_dbg : std_logic_vector(47 downto 0);
signal regs_ila : std_logic_vector(7 downto 0);
attribute keep_hierarchy of wr2rf_vme_p0_i : label is "yes";
attribute keep_hierarchy of inst_vme_core : label is "yes";
attribute keep_hierarchy of inst_RFFrameTransceiver : label is "yes";
attribute keep_hierarchy of inst_xwr_streamers : label is "yes";
--attribute keep_hierarchy of inst_WR_CORE : label is "yes";
begin
-- Poweron reset.
......@@ -800,6 +812,9 @@ begin
pps_led_o => open,
pps_csync_o => pps_csync,
rst_aux_n_o => open,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
link_ok_o => link_ok );
inst_xwr_streamers : entity work.xwr_streamers
......@@ -1368,6 +1383,8 @@ begin
ocxo_enabled_i => ocxo_enabled,
ocxo_uptime_o => ocxo_uptime );
-- timing_io
tmg_clk_oe_n_o <= not tmg_clk_oe_o;
tmg_io_oe_n_o <= not tmg_io_oe_o;
......@@ -1375,11 +1392,28 @@ begin
tmg_clk_o <= "00"; -- used for starts as input
tmg_io_o(1) <= '0'; -- used for stop as input
tmg_io_o(2) <= '0'; -- used for stop as input
tmg_io_o(3) <= rf1_frev when tmg_io_rf1_sel = '0' and tmg_frev_rf1_sel = '0' else
tmg_io(3) <= rf1_frev when tmg_io_rf1_sel = '0' and tmg_frev_rf1_sel = '0' else
rf1_frev_main when tmg_io_rf1_sel = '0' and tmg_frev_rf1_sel = '1' else rf_sync;
tmg_io_o(4) <= rf2_frev when tmg_io_rf2_sel = '0' and tmg_frev_rf2_sel = '0' else
tmg_io(4) <= rf2_frev when tmg_io_rf2_sel = '0' and tmg_frev_rf2_sel = '0' else
rf2_frev_main when tmg_io_rf2_sel = '0' and tmg_frev_rf2_sel = '1' else rf_sync;
inst_extend_pulse_tmg_3 : entity work.gc_extend_pulse
generic map (
g_width => 4 )
port map (
clk_i => clk125m,
rst_n_i => rst_clk125m_n,
pulse_i => tmg_io(3),
extended_o => tmg_io_o(3) );
inst_extend_pulse_tmg_4 : entity work.gc_extend_pulse
generic map (
g_width => 4 )
port map (
clk_i => clk125m,
rst_n_i => rst_clk125m_n,
pulse_i => tmg_io(4),
extended_o => tmg_io_o(4) );
-- debug
ila_sigs(0) <= clk_sys_select;
ila_sigs(1) <= clk_sys_reset;
......@@ -1401,7 +1435,10 @@ begin
ila_sigs(15) <= wb_wrc_out.ack;
--ila_sigs(111 downto 16) <= rfnco1_ila_dbg;
ila_sigs(63 downto 16) <= vme_dbg;
ila_sigs(111 downto 64) <= (others => '0');
ila_sigs(71 downto 64) <= rft1_ila_dbg;
ila_sigs(79 downto 72) <= rft2_ila_dbg;
ila_sigs(111 downto 80) <= (others => '0');
--ila_sigs(111 downto 64) <= (others => '0');
ila_sigs(112) <= wb_rf1_rfnco_out.stb;
ila_sigs(113) <= wb_rf1_rfnco_out.we;
ila_sigs(114) <= wb_rf1_rfnco_in.ack;
......@@ -1420,7 +1457,8 @@ begin
ila_sigs(127) <= rf1_frev_main;
--ila_clk <= clk250m;
ila_clk <= clk_sys_62m5;
--ila_clk <= clk_sys_62m5;
ila_clk <= clk125m;
ila_i : entity work.ila
generic map (
......
software/libwr2rf/wr2rf.c
View file @ 9224773d
......@@ -119,16 +119,21 @@ static void
framerxtx_send1 (struct libwr2rf_dev *dev, int argc, char **argv)
{
unsigned long long ftw_h1 = 0x16B24A8FB6ULL;
unsigned control = 0;
unsigned control_1 = 0;
unsigned control_2 = 0;
unsigned pulse = 0;
unsigned i;
for (i = 1; i < argc; i++) {
if (strcmp(argv[i], "reset") == 0)
control |= 1;
else if (isdigit(argv[i][0]))
control_1 |= 1;
else if (strcmp(argv[i], "pulse") == 0) {
control_1 |= 1;
pulse = 1;
} else if (isdigit(argv[i][0]))
ftw_h1 = strtoull(argv[i], NULL, 0);
else {
printf ("usage: %s [FTW] [reset] \n", argv[0]);
printf ("usage: %s [FTW] [reset] [pulse]\n", argv[0]);
return;
}
}
......@@ -137,10 +142,15 @@ framerxtx_send1 (struct libwr2rf_dev *dev, int argc, char **argv)
libwr2rf_write16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_TXFRAME_FTW_H1_MAIN + 2, ftw_h1 >> 32);
libwr2rf_write16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_TXFRAME_FTW_H1_MAIN + 4, ftw_h1 >> 16);
libwr2rf_write16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_TXFRAME_FTW_H1_MAIN + 6, ftw_h1 >> 0);
libwr2rf_write16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_TXFRAME_CONTROL, control);
libwr2rf_write16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_TXFRAME_CONTROL, control_1);
/* SCR: tx dbg=2 (simulation), ftype=1 (RFm), send-once. */
libwr2rf_framerxtx_write32 (dev, 0x04, (1 << 3) | (0 << 1) | (1 << 0));
if (pulse) {
libwr2rf_write16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_TXFRAME_CONTROL, control_2);
libwr2rf_framerxtx_write32 (dev, 0x04, (1 << 3) | (0 << 1) | (1 << 0));
}
}
static void
......@@ -1488,6 +1498,37 @@ dac_ram (struct libwr2rf_dev *dev, int argc, char **argv)
}
}
static void
disp_tmg(struct libwr2rf_dev *dev)
{
unsigned addr = WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_TMG;
unsigned val;
unsigned i;
val = libwr2rf_read16(dev, addr);
printf ("Complete TMG register: tmg[11:0]=%03x\n", val);
printf (" tmg io term:");
for (i = 0; i < 4; i++)
printf (" %u:%u",
i, (val >> (WR2RF_INIT_REGS_TMG_IO_TERM_SHIFT + i)) & 1);
printf ("\n");
printf (" tmg io oen: ");
for (i = 0; i < 4; i++)
printf (" %u:%u",
i, (val >> (WR2RF_INIT_REGS_TMG_IO_OE_SHIFT + i)) & 1);
printf ("\n");
printf (" tmg clk term:");
for (i = 0; i < 2; i++)
printf (" %u:%u",
i, (val >> (WR2RF_INIT_REGS_TMG_CLK_TERM_SHIFT + i)) & 1);
printf ("\n");
printf (" tmg clk oen: ");
for (i = 0; i < 2; i++)
printf (" %u:%u",
i, (val >> (WR2RF_INIT_REGS_TMG_CLK_OE_SHIFT + i)) & 1);
printf ("\n");
}
static void
tmgio_oe (struct libwr2rf_dev *dev, int argc, char **argv)
{
......@@ -1508,8 +1549,7 @@ tmgio_oe (struct libwr2rf_dev *dev, int argc, char **argv)
libwr2rf_write16(dev, addr, bval);
}
val = libwr2rf_read16(dev, addr);
printf ("Complete TMG register: tmg[11:0]=%02x\n", val);
disp_tmg(dev);
}
static void
......@@ -1532,8 +1572,7 @@ tmgio_term (struct libwr2rf_dev *dev, int argc, char **argv)
libwr2rf_write16(dev, addr, bval);
}
val = libwr2rf_read16(dev, addr);
printf ("Complete TMG register: tmg[11:0]=%02x\n", val);
disp_tmg(dev);
}
static void
......@@ -1626,8 +1665,7 @@ tmgclk_term (struct libwr2rf_dev *dev, int argc, char **argv)
libwr2rf_write16(dev, addr, bval);
}
val = libwr2rf_read16(dev, addr);
printf ("Complete TMG register: tmg[11:0]=%02x\n", val);
disp_tmg(dev);
}
static void
......@@ -1650,14 +1688,10 @@ tmgclk_oe (struct libwr2rf_dev *dev, int argc, char **argv)
libwr2rf_write16(dev, addr, bval);
}
val = libwr2rf_read16(dev, addr);
printf ("Complete TMG register: tmg[11:0]=%02x\n", val);
disp_tmg(dev);
}
static void
disp_vtudiag(struct libwr2rf_dev *dev, unsigned addr)
{
......@@ -1754,7 +1788,7 @@ rf_diag (struct libwr2rf_dev *dev, int argc, char **argv)
unsigned addr;
if (argc < 2) {
printf ("usage: rf-diag 1|2\n");
printf ("usage: rf-diag 1|2 CMD\n");
return;
}
......@@ -1841,13 +1875,7 @@ vtu (struct libwr2rf_dev *dev, int argc, char **argv)
(unsigned)(v & TRIGUNIT_REGS_STATUS_WRONGWVALUE));
v = libwr2rf_read16(dev, addr + TRIGUNIT_REGS_CONTROL);
printf ("control: 0x%04x\n", v);
printf (" vtureset: 0x%04x\n",
(unsigned)(v & TRIGUNIT_REGS_CONTROL_VTURESET));
printf (" stopsofttrigger : 0x%04x\n",
(unsigned)(v & TRIGUNIT_REGS_CONTROL_STOPSOFTTRIGGER));
printf (" startsofttrigger: 0x%04x\n",
(unsigned)(v & TRIGUNIT_REGS_CONTROL_STARTSOFTTRIGGER));
printf ("vtureset: %u\n", !!(v & TRIGUNIT_REGS_CONTROL_VTURESET));
v = libwr2rf_read16(dev, addr + TRIGUNIT_REGS_CONFIGOFFLINE);
printf ("configoffline: 0x%04x\n", v);
......@@ -1931,9 +1959,11 @@ vtu (struct libwr2rf_dev *dev, int argc, char **argv)
mode = 0x04;
else if (strcmp (argv[3], "play") == 0)
mode = 0x05;
else if (strcmp (argv[3], "highfreq") == 0)
mode = 0x06;
else {
printf ("bad vtu mode, expect: "
"pulse, infinite, window, syncless, lowfreq, play\n");
"pulse, infinite, window, syncless, lowfreq, play, highfreq\n");
return;
}
v = libwr2rf_read16(dev, addr + TRIGUNIT_REGS_CONFIGOFFLINE);
......@@ -1968,6 +1998,7 @@ vtu (struct libwr2rf_dev *dev, int argc, char **argv)
}
else {
printf("usage: vtu RF.TR Display registers\n");
printf("usage: vtu RF.TR diag ... Diagnostic\n");
printf("usage: vtu RF.TR b VAL Set offline bvalue\n");
printf("usage: vtu RF.TR ht VAL Set offline htvalue\n");
printf("usage: vtu RF.TR w VAL Set offline wvalue\n");
......@@ -2039,7 +2070,7 @@ vtu_out (struct libwr2rf_dev *dev, int argc, char **argv)
else {
printf ("usage: %s RF.TR [CMD]\n", argv[0]);
printf ("commands are:\n");
printf (" oen 0|1\n");
printf (" oen 0|1 [0: enable, 1: disable]\n");
printf (" shape 0|1\n");
}
}
......
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