Commit a4502ea7 authored by Tristan Gingold's avatar Tristan Gingold

wr2rf_vme: add new wr_eeprom ports.

parent 89f2d5ce
...@@ -141,8 +141,10 @@ entity wr2rf_vme is ...@@ -141,8 +141,10 @@ entity wr2rf_vme is
spi_flash_mosi_o : out std_logic; spi_flash_mosi_o : out std_logic;
-- WR eeprom -- WR eeprom
wr_eeprom_scl_b : inout std_logic; wr_eeprom1_scl_b : inout std_logic;
wr_eeprom_sda_b : inout std_logic; wr_eeprom1_sda_b : inout std_logic;
wr_eeprom2_scl_b : inout std_logic;
wr_eeprom2_sda_b : inout std_logic;
-- Onewire -- Onewire
wr_onewire_b : inout std_logic; wr_onewire_b : inout std_logic;
...@@ -650,10 +652,13 @@ begin ...@@ -650,10 +652,13 @@ begin
owr_i(0) <= wr_onewire_b; owr_i(0) <= wr_onewire_b;
owr_i(1) <= '1'; owr_i(1) <= '1';
wr_eeprom_scl_b <= '0' when wr1_scl_out = '0' else 'Z'; wr_eeprom1_scl_b <= '0' when wr1_scl_out = '0' else 'Z';
wr_eeprom_sda_b <= '0' when wr1_sda_out = '0' else 'Z'; wr_eeprom1_sda_b <= '0' when wr1_sda_out = '0' else 'Z';
wr1_scl_in <= wr_eeprom_scl_b; wr1_scl_in <= wr_eeprom1_scl_b;
wr1_sda_in <= wr_eeprom_sda_b; wr1_sda_in <= wr_eeprom1_sda_b;
wr_eeprom2_scl_b <= 'Z';
wr_eeprom2_sda_b <= 'Z';
process(clk_sys_62m5) process(clk_sys_62m5)
begin begin
......
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