Commit a578965d authored by Tristan Gingold's avatar Tristan Gingold

tb_vtu: Add abstractions.

parent b5aa3837
......@@ -143,6 +143,45 @@ begin
end process;
process
-- Send a pulse on the start signal and wait until it is propagated to the VTU.
procedure start_pulse is
begin
-- Start pulse.
start <= '1';
wait for 40 ns;
start <= '0';
-- Wait until the VTU get the start pulse
for i in 1 to 7 loop
wait until rising_edge(clk_vtu);
end loop;
end start_pulse;
procedure sync_pulse is
begin
sync <= '1';
wait for 10 ns;
sync <= '0';
-- Wait until the VTU get the sync pulse.
for i in 1 to 3 loop
wait until rising_edge(clk_vtu);
end loop;
end sync_pulse;
procedure read_status (s : inout std_logic_vector(15 downto 0)) is
begin
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_STATUS, s);
report "status = " & to_string(s)
& ", missvalid=" & to_string (s (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET))
& ", missready=" & to_string (s (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET))
& ", startready=" & to_string (s (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET))
& ", running=" & to_string (s (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET));
-- assert s (TRIGUNIT_REGS_STATUS_WRONGBVALUE_OFFSET) = '0' severity error;
-- assert s (TRIGUNIT_REGS_STATUS_WRONGHTVALUE_OFFSET) = '0' severity error;
-- assert s (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '0' severity error;
end read_status;
variable val : std_logic_vector(15 downto 0);
begin
sync <= '0';
......@@ -168,8 +207,7 @@ begin
write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONTROL, x"0000");
-- Check status.
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_STATUS, val);
report "status = " & to_string(val);
read_status(val);
assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
......@@ -184,21 +222,14 @@ begin
report "config online = " & to_string(val);
assert val = x"0000" severity error;
-- Expect 64 syncs.
observer_cmd <= (count => 64);
-- Start pulse.
start <= '1';
wait for 40 ns;
start <= '0';
-- Wait until the VTU get the start pulse
for i in 1 to 7 loop
wait until rising_edge(clk_vtu);
end loop;
start_pulse;
-- Check status.
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_STATUS, val);
report "status = " & to_string(val);
read_status(val);
assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
-- Should be 0 if close enough to the start pulse.
......@@ -209,17 +240,10 @@ begin
assert val (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '0' severity error;
-- Sync pulse.
sync <= '1';
wait for 10 ns;
sync <= '0';
sync_pulse;
-- Check ...
-- Wait until the VTU get the sync pulse.
for i in 1 to 3 loop
wait until rising_edge(clk_vtu);
end loop;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_STATUS, val);
report "status = " & to_string(val);
read_status(val);
assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '1' severity error;
......@@ -248,11 +272,18 @@ begin
assert observer_state = OBS_DONE severity error;
assert observer_period = 8 * 5 ns;
-- Check VTU status.
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_STATUS, val);
report "status = " & to_string(val);
read_status(val);
assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
-- Second test: check that missing valid parameters is reported.
-- (A cycle has been finished, the start signal has to be ignored because
-- parameters aren't set.)
start_pulse;
read_status(val);
assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '1' severity error;
report "end of tests";
wait;
end process;
......
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