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wr2rf-vme
Commit a9b7b1db authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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top: several timing hacks/optimizations 

- quieten down a number of single-ended I/Os (minimize current drive)
- get rid of MMCM on the DDMTD reference clock(!)
- floorplanning of the DDMTDs
parent df4dcc84
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Showing with 215 additions and 83 deletions
wr-cores @ 23ce67f0
Subproject commit 1ee142a3830995ea2e940165b3b86fb95667b019
Subproject commit 23ce67f04627ba14b0bcabc9bd1114beb47e8bf3
hdl/rtl/wr2rf_sysclks.vhd
View file @ a9b7b1db
......@@ -39,6 +39,7 @@ entity wr2rf_sysclks is
mmcm_shift_en_i : in std_logic;
mmcm_shift_busy_o : out std_logic;
clk62m5_o : out std_logic;
rst_clk62m5_n_o : out std_logic;
rst_clk62m5_o : out std_logic;
......
hdl/syn/wr2rf_vme/wr2rf_vme.tcl
View file @ a9b7b1db
......@@ -32,26 +32,29 @@ read_xdc $projDir/gencores_constraints.xdc
set start_time [clock seconds]
#synth_design -rtl -top ${top} -part ${device} > ${top}_synth.log
synth_design -top ${top} -part ${device} -generic g_hwbld_date=${start_time} > ${top}_synth.log
synth_design -top ${top} -part ${device} -generic g_hwbld_date=${start_time}
#> ${top}_synth.log
write_checkpoint -force ${top}_synth
#source wr2rf_async_regs.tcl
#source wr2rf_maxdelays.tcl
#source wr2rf_dmtd_falsepath.tcl
source wr2rf_t1sync_falsepath.tcl
#source wr2rf_t1sync_falsepath.tcl
#opt_design -directive Explore -verbose > ${top}_opt.log
#write_checkpoint -force ${top}_opt
#place_design -directive Explore > ${top}_place.log
place_design > ${top}_place.log
place_design
#> ${top}_place.log
place_design -post_place_opt
write_checkpoint -force ${projDir}/${top}_place
#phys_opt_design -directive Explore > ${top}_phys_opt.log
#write_checkpoint -force ${projDir}/${top}_phys_opt
route_design > ${top}_route.log
route_design
#> ${top}_route.log
write_checkpoint -force ${projDir}/${top}_route
source wr2rf_cdc_waivers.tcl
......@@ -63,8 +66,8 @@ report_utilization -hierarchical -file ${top}_utilization.rpt
report_io -file ${top}_pin.rpt
# Some reports to monitor min/max delays on key outputs plus skew for the iqdac data lines
source wr2rf_triggers.tcl
source wr2rf_iqdac_skew.tcl
#source wr2rf_triggers.tcl
#source wr2rf_iqdac_skew.tcl
# bitstream configuration...
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]
......
hdl/syn/wr2rf_vme/wr2rf_vme.xdc
View file @ a9b7b1db
This diff is collapsed.
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ a9b7b1db
......@@ -44,8 +44,8 @@ entity wr2rf_vme is
generic (
g_simulation : integer := 0;
g_dpram_size : integer := 131072/4;
g_dpram_initf : string := "../../../../dependencies/wrpc-sw-file/wrc.bram";
-- g_dpram_initf : string := "";
-- g_dpram_initf : string := "../../../../dependencies/wrpc-sw-file/wrc.bram";
g_dpram_initf : string := "";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -320,7 +320,7 @@ architecture rtl of wr2rf_vme is
signal rst_sys_r : std_logic;
signal rst_sys_n : std_logic;
signal rst_sys : std_logic;
signal clk_ref_62m5 : std_logic;
signal clk62m5 : std_logic;
signal clk125m : std_logic;
signal clk200m : std_logic;
......@@ -387,10 +387,14 @@ architecture rtl of wr2rf_vme is
signal pps_p : std_logic;
signal pps_csync : std_logic;
signal dac_hpll_load_p1_o : std_logic;
signal dac_dpll_load_p1_o : std_logic;
signal dac_hpll_data_o : std_logic_vector(15 downto 0);
signal dac_dpll_data_o : std_logic_vector(15 downto 0);
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(23 downto 0);
signal dac_dpll_data : std_logic_vector(23 downto 0);
signal dac_hpll_dither_load_p1 : std_logic;
signal dac_dpll_dither_load_p1 : std_logic;
signal dac_hpll_dither_data : std_logic_vector(15 downto 0);
signal dac_dpll_dither_data : std_logic_vector(15 downto 0);
signal sfp1_scl_out : std_logic;
signal sfp1_scl_in : std_logic;
......@@ -734,12 +738,18 @@ begin
----------------------------------------------------------------------------
inst_IBUFDS_dmtd : IBUFGDS
generic map (
IBUF_LOW_PWR => FALSE
)
port map (
O => clk_dmtd_62m5, -- Buffer output
I => clk_dmtd_62m5_p_i, -- Diff_p buffer input
IB => clk_dmtd_62m5_n_i ); -- Diff_n buffer input
inst_IBUFDS_sys : IBUFGDS
generic map (
IBUF_LOW_PWR => FALSE
)
port map (
O => clk_sys_62m5_in,
I => clk_sys_62m5_p_i,
......@@ -752,6 +762,8 @@ begin
I1 => clk62m5, -- 1-bit input: Clock input (S=1)
S => clk_sys_select ); -- 1-bit input: Clock select
clk_ref_62m5 <= clk_sys_62m5_in;
inst_IBUFDS_clk_ext_10m : IBUFGDS
port map (
O => clk_ext_10m_in, -- Buffer output
......@@ -838,13 +850,14 @@ begin
inst_GTX_Link0 : entity work.wr_gtx_phy_kintex7_lp
generic map(
g_simulation => g_simulation)
g_simulation => g_simulation,
g_reverse_ddmtds => true)
port map(
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => wrcore_reset_n,
clk_gtx_i => clk_gtx_125m,
clk_dmtd_i => clk_dmtd_62m5,
clk_ref_i => clk_sys_62m5,
clk_ref_i => clk_ref_62m5,
tx_clk_o => open,
tx_locked_o => open,
tx_data_i => phy16_out.tx_data,
......@@ -881,6 +894,7 @@ begin
g_vuart_fifo_size => 1024,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dac_bits => 24,
g_tx_runt_padding => true,
g_records_for_phy => true,
g_pcs_16bit => true,
......@@ -891,6 +905,7 @@ begin
g_aux_sdb => c_wrc_periph3_sdb,
g_softpll_enable_debugger => true,
g_softpll_use_sampled_ref_clocks => true,
g_softpll_reverse_dmtds => true,
g_diag_id => c_diag_id,
g_diag_ver => c_diag_ver,
g_diag_ro_size => c_diag_ro_size,
......@@ -899,7 +914,7 @@ begin
port map(
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => clk_dmtd_62m5,
clk_ref_i => clk_sys_62m5, --clk_125m_ref,
clk_ref_i => clk_ref_62m5, --clk_125m_ref,
clk_aux_i(0) => clk_aux_in,
clk_ext_i => clk_ext_10m,
clk_ext_mul_i => clk_ext_mul,
......@@ -908,10 +923,10 @@ begin
clk_ext_rst_o => clk_ext_rst,
pps_ext_i => pps_i,
rst_n_i => wrcore_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1_o,
dac_hpll_data_o => dac_hpll_data_o,
dac_dpll_load_p1_o => dac_dpll_load_p1_o,
dac_dpll_data_o => dac_dpll_data_o,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
phy16_i => phy16_in,
phy16_o => phy16_out,
phy_mdio_master_o => phy_mdio_out,
......@@ -1239,6 +1254,21 @@ begin
rf1_ila_dbg_o => rfnco1_ila_dbg,
rf2_ila_dbg_o => rfnco2_ila_dbg );
inst_dac_driver_main : entity work.wrc_dac_driver
generic map (
g_dither_amplitude_log2 => 8,
g_dither_clock_div_log2 => 9,
g_dither_init_value => x"deadbeef")
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_n,
x_valid_i => dac_dpll_load_p1,
x_i => dac_dpll_data,
y_o => dac_dpll_dither_data,
y_valid_o => dac_dpll_dither_load_p1);
inst_ocxo_DAC : entity work.gc_serial_dac
generic map (
g_num_data_bits => 16,
......@@ -1248,14 +1278,28 @@ begin
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_n,
value_i => dac_dpll_data_o,
value_i => dac_dpll_dither_data,
cs_sel_i => "1",
load_i => dac_dpll_load_p1_o,
load_i => dac_dpll_dither_load_p1,
sclk_divsel_i => "010",
dac_cs_n_o(0) => wr_dac_ocxo_cs_n_o,
dac_sclk_o => wr_dac_ocxo_sclk_o,
dac_sdata_o => wr_dac_ocxo_din_o);
inst_dac_driver_helper : entity work.wrc_dac_driver
generic map (
g_dither_amplitude_log2 => 8,
g_dither_clock_div_log2 => 9,
g_dither_init_value => x"cafebabe")
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_n,
x_valid_i => dac_hpll_load_p1,
x_i => dac_hpll_data,
y_o => dac_hpll_dither_data,
y_valid_o => dac_hpll_dither_load_p1);
inst_dmtd_DAC : entity work.gc_serial_dac
generic map (
g_num_data_bits => 16,
......@@ -1265,9 +1309,9 @@ begin
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_n,
value_i => dac_hpll_data_o,
value_i => dac_hpll_dither_data,
cs_sel_i => "1",
load_i => dac_hpll_load_p1_o,
load_i => dac_hpll_dither_load_p1,
sclk_divsel_i => "010",
dac_cs_n_o(0) => wr_dac_dmtd_cs_n_o,
dac_sclk_o => wr_dac_dmtd_sclk_o,
......@@ -1420,8 +1464,8 @@ begin
rf_t1_start_i => rf1_t1_start,
rf_t1_stop_i => rf1_t1_stop,
rf_t2_clk_p_i => rf1_t2_clk_p_i,
rf_t2_clk_n_i => rf1_t2_clk_n_i,
rf_t2_clk_p_i => '0',--rf1_t2_clk_p_i,
rf_t2_clk_n_i => '0',--rf1_t2_clk_n_i,
rf_t2_p_o => rf1_t2_p_o,
rf_t2_n_o => rf1_t2_n_o,
rf_t2_rst_i => rf1_t2_rst,
......@@ -1478,8 +1522,8 @@ begin
rf_t1_start_i => rf2_t1_start,
rf_t1_stop_i => rf2_t1_stop,
rf_t2_clk_p_i => rf2_t2_clk_p_i,
rf_t2_clk_n_i => rf2_t2_clk_n_i,
rf_t2_clk_p_i => '0',--rf2_t2_clk_p_i,
rf_t2_clk_n_i => '0',--rf2_t2_clk_n_i,
rf_t2_p_o => rf2_t2_p_o,
rf_t2_n_o => rf2_t2_n_o,
rf_t2_rst_i => rf2_t2_rst,
......
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