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wr2rf-vme
Commit bd08f811 authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: remove RestartEnable (always 0)

parent 3647dfb5
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Showing with 0 additions and 24 deletions
dependencies/vtu/rtl/vtuCore.vhd
View file @ bd08f811
......@@ -777,7 +777,6 @@ entity vtuSeq is
SwitchtoHT : out std_logic := '0';
wValueOne : in std_logic;
WindowDone : in std_logic;
RestartEnable : in std_logic;
CounterRst : out std_logic := '0';
Run : out std_logic := '0'
);
......@@ -786,15 +785,9 @@ end vtuSeq;
architecture vtuSeq of vtuSeq is
type visual_Idle_states is (Idle, S_BValue, S_HTValue, S_waitSync);
signal visual_Idle_current : visual_Idle_states;
begin
-- Synchronous process
vtuSeq_Idle:
process (Clk)
......@@ -875,19 +868,6 @@ begin
CounterRst <= '1';
Run <= '0';
visual_Idle_current <= Idle;
elsif (RestartEnable = '1' and Start = '1' and SyncPulse = '0') then
Shifter1Ena <= '1';
Shifter2Ena <= '0';
SwitchtoHT <= '0';
CounterRst <= '1';
Run <= '0';
visual_Idle_current <= S_waitSync;
elsif (RestartEnable = '1' and Start = '1' and SyncPulse = '1') then
Shifter1Ena <= '1';
Shifter2Ena <= '1';
SwitchtoHT <= '0';
CounterRst <= '1';
visual_Idle_current <= S_BValue;
else
visual_Idle_current <= S_HTValue;
end if;
......@@ -1318,7 +1298,6 @@ architecture vtuCore of vtuCore is
signal FilledMuxSel : std_logic;
signal DataOut_seq_i : std_logic_vector(7 downto 0 );
signal RunSyncLess : std_logic;
signal RestartEnable : std_logic;
signal wrongValue : std_logic;
signal SwitchHTeffective_n : std_logic;
signal ClkValueSwitch_n : std_logic;
......@@ -1465,7 +1444,6 @@ begin
SwitchtoHT => SwitchtoHT,
wValueOne => wValueOne_seq,
WindowDone => WindowDone_seq,
RestartEnable => RestartEnable,
CounterRst => counterReset,
Run => Run_seq
);
......@@ -1747,8 +1725,6 @@ begin
SwitchOutput <= SwitchtoHT or (not Run_seq);
RestartEnable <= '0';
InfiniteWindow <= InfiniteWindowMode or LowFreqGenerationMode;
process (DataOut_seq_i, AllZeroOut, RstOrStopSeq)
......
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