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wr2rf-vme
Commit eaa7b13d authored by Tristan Gingold's avatar Tristan Gingold
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Add top file, manifests, dependencies.

parent c89720a1
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.gitmodules 0 → 100644
View file @ eaa7b13d
[submodule "dependencies/general-cores"]
path = dependencies/general-cores
url = git://ohwr.org/project/general-cores.git
[submodule "dependencies/vme64x-core"]
path = dependencies/vme64x-core
url = git://ohwr.org/project/vme64x-core.git
general-cores @ be61ce73
Subproject commit be61ce73a43d0231e8edc2f12133b918e3d1c9e4
vme64x-core @ 6abee52c
Subproject commit 6abee52c1b5f3c2a40e202eb9f5890c05e0d7f66
hdl/syn/Manifest.py 0 → 100644
View file @ eaa7b13d
action = "synthesis"
syn_device = "xc7k70t"
syn_grade = "-2"
syn_package = "fbg676"
syn_top = "wr2rf_vme"
syn_project = "wr2rf_vme"
syn_tool = "vivado"
target = "xilinx"
modules = {'local': ['../top']}
hdl/top/Manifest.py 0 → 100644
View file @ eaa7b13d
files = ['wr2rf_vme.vhd']
modules = {'local': [ '../rtl' ],
'git': [ "git://ohwr.org/project/general-cores.git",
"git://ohwr.org/project/vme64x-core.git"] }
hdl/rtl/wr2rf_vme.vhd → hdl/top/wr2rf_vme.vhd
View file @ eaa7b13d
......@@ -26,8 +26,21 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
entity wr2rf_vme is
port (
-- Reset from system fpga
rst_n_i : in std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
---------------------------------------------------------------------------
-- VME interface D16 A24
-- Note: retry, berr not required
......@@ -61,5 +74,148 @@ entity wr2rf_vme is
end wr2rf_vme;
architecture rtl of wr2rf_vme is
signal pllout_clk_fb_sys, pllout_clk_sys : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_sys : std_logic;
signal local_reset_n : std_logic;
signal powerup_rst_n : std_logic := '0';
signal sys_locked : std_logic;
-- Wishbone bus from master
signal master_out : t_wishbone_master_out;
signal master_in : t_wishbone_master_in;
-- VME
signal vme_data_b_out : std_logic_vector(15 downto 0);
signal vme_data_b_out1 : std_logic_vector(31 downto 16);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_addr_oe_n : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n_o : std_logic;
signal vme_irq_n_o : std_logic_vector(7 downto 1);
begin
-------------------------------------------------------------------------------
-- Clock distribution/PLL and reset
-------------------------------------------------------------------------------
-- Input is 20Mhz
U_cmp_sys_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 1Ghz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_sys,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open, -- pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_sys,
CLKIN => clk_20m_vcxo_buf);
U_Sync_Reset : entity work.gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => powerup_rst_n,
synced_o => local_reset_n);
U_cmp_clk_vcxo_buf : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
U_cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
-----------------------------------------------------------------------------
-- VME64x Core and buffers
-----------------------------------------------------------------------------
-- BERR and IRQ vme signals are inverted by the drivers. See schematics.
vme_berr_o <= not vme_berr_n_o;
vme_irq_o <= not vme_irq_n_o;
inst_vme_core : entity work.xvme64x_core
generic map (
g_CLOCK_PERIOD => 8,
g_VME32 => False,
g_ENABLE_CR_CSR => False,
g_USER_CSR_EXT => False,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID,
g_DECODER => (0 => (adem => x"fff00000", amcap => x"ee000000_00000000", dawpr => x"83"),
others => (adem => x"00000000", amcap => x"00000000_00000000", dawpr => x"83"))
)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_sysreset_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_i,
vme_i.addr (23 downto 1) => vme_addr_i (23 downto 1),
vme_i.addr (31 downto 24) => x"00",
vme_i.data (15 downto 0) => vme_data_b (15 downto 0),
vme_i.data (31 downto 16) => x"0000",
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n_o,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data (15 downto 0) => vme_data_b_out,
vme_o.data (31 downto 16) => vme_data_b_out1,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n_o,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n,
wb_i => master_in,
wb_o => master_out);
vme_ga <= vme_gap_i & vme_ga_i;
-- VME tri-state buffers
vme_data_b (15 downto 0) <= vme_data_b_out when vme_data_dir_int = '1'
else (others => 'Z');
vme_data_dir_o <= vme_data_dir_int;
end rtl;
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